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Circuit for programmable stepless clock shifting

  • US 6,995,593 B2
  • Filed: 11/25/2003
  • Issued: 02/07/2006
  • Est. Priority Date: 02/21/2003
  • Status: Active Grant
First Claim
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1. A circuit for programmable stepless clock shifting comprising:

  • a splitter, receiving a clock reference and generating two 90°

    -shifted clock phases, said;

    splitter comprising a delay circuit receiving said clock reference and supplying a delayed clock;

    an adder and a subtractor of said clock reference and said delayed clock, supplying at the output said two 90°

    -shifted clock phases, and two squarers for squaring said two 90°

    -shifted clock phases, so that said two 90°

    -shifted clock phases have the same amplitude as one another; and

    an interpolator receiving said two 90°

    -shifted clock phases from said squarers and two coefficients, and supplying a programmable phase clock, which has a phase shift with respect to said clock reference that depends only on said two coefficients.

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