Circuit for programmable stepless clock shifting

• US 6,995,593 B2
• Filed: 11/25/2003
• Issued: 02/07/2006
• Est. Priority Date: 02/21/2003
• Status: Active Grant

• Current Assignee: Alcatel SA (Nokia Corporation)
• Original Assignee: Alcatel SA (Nokia Corporation)
• Inventors: Novellini, Paolo, Cucchi, Silvio
• Primary Examiner(s): LAM, TUAN THIEU
• Application Number:
  US10/720,195
• Publication Number:
  US 20040164779A1
• Time in Patent Office: 805 Days
• Field of Search: 327/231, 327/233, 327/234, 327/237, 327/238, 327/248, 327/254, 327/255
• US Class Current: 327/238
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03K 2005/00026 controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
• CPC Class Codes: H03K 2005/00286 Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency

Abstract

The present invention provides for a circuit for programmable stepless clock shifting, consisting of a splitter generating a 0° and a 90° shifted clocks from a reference clock, and an interpolator of the two shifted clocks, which provides at the output the desired pre-set clock phase.

Claims

1. A circuit for programmable stepless clock shifting comprising:

a splitter, receiving a clock reference and generating two 90°

-shifted clock phases, said;

splitter comprising a delay circuit receiving said clock reference and supplying a delayed clock;

an adder and a subtractor of said clock reference and said delayed clock, supplying at the output said two 90°

-shifted clock phases, and two squarers for squaring said two 90°

-shifted clock phases, so that said two 90°

-shifted clock phases have the same amplitude as one another; and

an interpolator receiving said two 90°

-shifted clock phases from said squarers and two coefficients, and supplying a programmable phase clock, which has a phase shift with respect to said clock reference that depends only on said two coefficients.

2. A circuit according to claim 1 wherein the delay introduced by said delay circuit is typically Δ

=90°

±

50%, and is

Δ

≠

π

+kπ

, k={0, ±

1, ±

2 . . . }.

3. A circuit according to claim 1, wherein said interpolator comprises:

a first and second multiplier, respectively receiving one of said two 90°

-shifted clock phases and a first and second coefficient; and

an adder receiving the outputs of said first and second multiplier and supplying said programmable phase clock.

4. A circuit according to claim 3, wherein said first and second coefficients have a value of respectively sin Φ

and cos Φ

, such that the following relationship is performed;

sin(ω

t+Φ

)=sin(ω

t)cos Φ

+cos(ω

t)sin Φ

where

Φ

is said programmable phase of the programmable phase clock;

sin(ω

t+Φ

) is the frequency of said programmable phase clock; and

sin(ω

t) and cos(ω

t) are the frequencies of said two 90°

-shifted clock phases.

5. A circuit according to claim 3, wherein said first and second coefficients are selected from a memory table, addressed according to the desired programmable phase.

6. A circuit according to claim 4, wherein said first and second coefficient are selected from a memory table, addressed according to the desired programmable phase.