Phase interpolator device and method

• US 6,995,594 B2
• Filed: 05/28/2004
• Issued: 02/07/2006
• Est. Priority Date: 04/28/2000
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Wakayama, Myles, Wang, Hui, Baumer, Howard A., Jiang, Xicheng, Le, Michael, Buchwald, Aaron W., Van Engelen, Jurgen, Madisetti, Avanindra
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): COX, CASSANDRA F
• Application Number:
  US10/855,392
• Publication Number:
  US 20040212416A1
• Time in Patent Office: 620 Days
• Field of Search: 327/248, 327/250, 327/231, 327233-235, 327/355, 327/361
• US Class Current: 327/248
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H04L 2025/03477 not time-recursive
• CPC Class Codes: H04L 2025/03617 Time recursive algorithms H04L2025/03643 takes precedence
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03885 adaptive
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0274 with Costas loop
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Claims

1. A phase interpolation method, comprising:

(a) producing a plurality of binary control signals in response to a phase control input;

(b) scaling each of a plurality of reference signals into a corresponding component signal in response to a corresponding plurality of binary control signals, wherein each of the reference signals has a distinct phase; and

(c) combining the component signals into an output signal having an interpolated phase,

wherein step (b) comprises converting each of four reference signals into a corresponding component signal in response to a respective plurality of binary control signals, wherein phases of the four reference signals are separated at substantially 90 degrees intervals.

4. The method of claim 1, wherein each of the component signals has a distinct phase determined by the corresponding reference signal phase.

5. The method of claim 1, wherein step (b) comprises:

scaling each reference signal into the corresponding component signal according to a scaling factor; and

adjusting the scaling factor in response to values of the corresponding binary control signals.

6. The method of claim 1, wherein step (c) comprises summing the component signals into an output signal having an interpolated phase.

7. The method of claim 1, wherein step (b) comprises converting a differential reference signal into a corresponding differential component signal;

and

wherein step (c) comprises combining the differential component signals into a differential output signal having an interpolated phase.

8. The method of claim 1, wherein step (a) comprises adjusting the plurality of binary control signals such that the output signal produced in step (c) is phase aligned with a serial data signal.

2. A phase interpolation method, comprising:

(a) producing a plurality of binary control signals in response to a phase control input;

(b) scaling each of a plurality of reference signals into a corresponding component signal in response to a corresponding plurality of binary control signals, wherein each of the reference signals has a distinct phase; and

(c) combining the component signals into an output signal having an interpolated phase,

wherein a value of each binary control signal is a sum of a plurality of control signals.

3. A phase interpolation method, comprising:

(a) producing a plurality of binary control signals in response to a phase control input;

(b) scaling each of a plurality of reference signals into a corresponding component signal in response to a corresponding plurality of binary control signals, wherein each of the reference signals has a distinct phase; and

(c) combining the component signals into an output signal having an interpolated phase,

wherein a value of a scaling factor used for scaling each of a plurality of reference signals increases with values of corresponding binary control signals.

9. A phase interpolation circuit, comprising:

stage controller means for producing binary control signals in response to a phase control input;

converting means for converting each of the plurality of reference signals into a corresponding component signal in response to a scaling factor, wherein each of the reference signals has a distinct phase;

scaling means, coupled to the converting means, for scaling the reference signals in response to values of the corresponding binary control signals; and

combining means for combining the component signals into an output signal having an interpolated phases,

wherein a value of a scaling factor used by the scaling means for scaling the reference signals increases with values of the corresponding binary control signals.

10. The circuit of claim 9, wherein each of the component signals has a distinct phase determined by the corresponding reference signal phase.