Methods, software, circuits and systems for coding information

• US 6,995,694 B1
• Filed: 06/20/2005
• Issued: 02/07/2006
• Est. Priority Date: 05/14/2004
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: He, Runsheng, Cheong, Kok-Wui
• Primary Examiner(s): JeanPierre, Peguy
• Assistant Examiner(s): Nguyen, Khai M.
• Application Number:
  US11/157,233
• Time in Patent Office: 232 Days
• Field of Search: 341 56- 59, 375/219, 375/286, 375/287, 375/292, 375/295, 375/298, 375/300, 375/316
• US Class Current: 341/58
• CPC Class Codes: H03M 5/145 Conversion to or from block codes or representations thereof
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0053 specially adapted for power saving

Abstract

Methods, software, circuits, architectures, and systems for encoding, decoding and error checking/correcting information, particularly pulse amplitude modulated information. The present invention enjoys particular advantage when used to encode x-unit sequence values of N-ary information into y-unit sequence values of M-ary information and to decode y-unit sequence values of M-ary information into x-unit sequence values of N-ary information, where N^x<M^y (and particularly where N^x<M^y, but N^x>M^y−M). The present invention advantageously provides a straight-forward mechanism for coding information that enables one to take advantage of coding overhead (e.g., unused states in the encoded, transmitted sequence) to accomplish other coding objectives, such as conforming to coding constraints, reducing transmission errors (or increasing the likelihood of successfully correcting such errors), dc balancing the coded information, and under certain conditions, even reducing power consumption.

Claims

1. An encoder, comprising:

a) a detector configured to identify each of a plurality of x-unit sequence values of an N-ary sequence, where x and N are each an integer of at least 2;

b) a converter configured to convert each of said x-unit N-ary sequence values to a y-unit M-ary sequence value, where y and M are each an integer of at least 2 and M^y>

N^x;

c) coding constraint logic configured to (i) determine whether an M-ary sequence output from said converter conforms to a coding constraint for said M-ary sequence and (ii) instruct said converter to output (1) a member of a first subset of y-unit M-ary sequence values when said M-ary sequence conforms to said coding constraint and (2) a member of a second subset of y-unit M-ary sequence values when said M-ary sequence violates said coding constraint, each of said y-unit M-ary sequence values in said second subset being distinct from said y-unit M-ary sequence values in said first subset.

2. The encoder of claim 1, wherein said converter comprises a first lookup table storing at least said first subset of y-unit M-ary sequence values.

3. The encoder of claim 2, wherein said converter further comprises a second lookup table storing said second subset of y-unit M-ary sequence values.

4. The encoder of claim 3, further comprising a multiplexer and/or selector configured to receive a signal from said coding constraint logic and select an output from said first lookup table when said M-ary sequence conforms to said coding constraint and from said second lookup table when said M-ary sequence violates said coding constraint.

5. The encoder of claim 1, further comprising a counter or incrementer configured to select one of said second subset of y-unit M-ary sequence values based on a value of an nth previous member of said second subset of y-unit M-ary sequence values, said nth previous member being different from a current member of said second subset of y-unit M-ary sequence values, and n being an integer of at least 1.

6. The encoder of claim 5, wherein said coding constraint logic comprises a memory or storage circuit configured to store the n previous member(s) of said second subset of y-unit M-ary sequence values.

7. The encoder of claim 6, wherein said coding constraint logic comprises a comparator configured to (i) receive a signal from the memory or storage circuit and (ii) identify the immediately previous member.

8. The encoder of claim 1, wherein each of said first subset of y-unit M-ary sequence values includes a transition.

9. The encoder of claim 1, wherein said coding constraint comprises a maximum number of consecutive same value units.

10. The encoder of claim 1, wherein N is 2, M is 3, x is 3, and y is 2.

11. A transmitter, comprising:

a) the encoder of claim 1; and

b) a modulator configured to transmit said M-ary sequence to a channel.

12. The transmitter of claim 1, further comprising a source encoder configured to receive a signal from an information source and/or input transducer, and provide said plurality of x-unit N-ary sequence values.

13. A transceiver, comprising:

a) the transmitter of claim 11; and

b) a receiver communicatively coupled to said channel, configured to process encoded information from said channel.

14. The transceiver of claim 13, wherein said receiver comprises a demodulator configured to receive said M-ary sequence from said channel.

15. The transceiver of claim 14, further comprising a decoder configured to decode said M-ary sequence.

16. The transceiver of claim 15, further comprising an output transducer configured to recover a signal from said decoded M-ary sequence.

17. A decoder, comprising:

a) a detector configured to identify a value of each of a plurality of y-unit M-ary sequences, where y and M are each an integer of at least 2;

b) a converter configured to convert said y-unit M-ary sequences to an x-unit N-ary sequence, where x and N are each an integer of at least 2, M^y>

N^x; and

c) coding constraint logic configured to (i) store a value for one to n previous y-unit M-ary sequences, n being an integer of at least 1, and (ii) instruct said converter to output one of a subset of x-unit N-ary sequence values based on said previous y-unit M-ary sequence value(s) when said detector identifies one of a subset of said y-unit M-ary sequence values.

18. The decoder of claim 17, wherein each member of said subset of y-unit M-ary sequence values consists of same value units.

19. The decoder of claim 17, wherein said coding constraint logic comprises a comparator configured to compare a current value of said one of said subset of y-unit M-ary sequence values to a value of a previous member of said subset of y-unit M-ary sequence values.

20. The decoder of claim 19, wherein said coding constraint logic is further configured to instruct said converter to output (1) a first one of said subset of x-unit N-ary sequence values if said current value differs from said value of said previous member and (2) a second one of said subset of x-unit N-ary sequence values if said current value equals said value of said previous member.

21. The decoder of claim 17, wherein said coding constraint logic is configured to (i) store an nth previous M-ary sequence value and (ii) instruct said converter to output an x-unit N-ary sequence value corresponding to said nth previous M-ary sequence value when said detector identifies said one of said subset of y-unit M-ary sequence values.

22. The decoder of claim 17, wherein N is 2, M is 3, x is 3, and y is 2.

23. The decoder of claim 17, wherein each of said y-unit M-ary sequence values other than said subset of y-unit M-ary sequence values includes a transition.

24. The decoder of claim 17, wherein said converter comprises a first look-up table configured to output said one of said subset of x-unit N-ary sequence values when said detector identifies said one of said subset of y-unit M-ary sequence values.

25. The decoder of claim 24, wherein said converter further comprises a second look-up table configured to output an x-unit N-ary sequence value other than one of said subset of x-unit N-ary sequence values when said detector identifies a y-unit M-ary sequence value other than one of said subset of y-unit M-ary sequence values.

26. The decoder of claim 25, further comprising further comprising a multiplexer and/or selector configured to receive a signal from said coding constraint logic and select an output from said second lookup table when said one of said subset of y-unit M-ary sequence values is identified and from said first lookup table when said y-unit M-ary sequence value other than one of said subset of y-unit M-ary sequence values is identified.

27. A receiver, comprising:

a) the decoder of claim 17; and

b) a demodulator communicatively coupled to said decoder, configured to receive encoded M-ary information from a channel.

28. The receiver of claim 27, further comprising a source decoder configured to decode said x-unit N-ary sequence values.

29. The receiver of claim 28, further comprising an output transducer configured to recover a signal from said decoded N-ary sequence.

30. A transceiver, comprising:

a) the receiver of claim 27; and

b) a transmitter communicatively coupled to said channel, configured to provide encoded information to said channel.

31. The transceiver of claim 30, wherein said transmitter comprises a modulator configured to transmit said M-ary sequence to said channel.

32. The transceiver of claim 31, further comprising an encoder configured to receive a signal from an information source and/or input transducer, and provide said plurality of y-unit M-ary sequence values.