Method for reducing dark current

• US 6,995,795 B1
• Filed: 09/12/2000
• Issued: 02/07/2006
• Est. Priority Date: 09/12/2000
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Eastman Kodak Company
• Inventors: Parks, Christopher, Losee, David L.
• Primary Examiner(s): Tran, Thai
• Assistant Examiner(s): Hannett, James M.
• Application Number:
  US09/660,105
• Time in Patent Office: 1,974 Days
• Field of Search: 348/312, 348/243, 348/320, 377/58
• US Class Current: 348/243
• CPC Class Codes: H01L 27/14806 Structural or functional details thereof
• CPC Class Codes: H01L 27/14843 Interline transfer
• CPC Class Codes: H04N 25/63 applied to dark current

Abstract

A method for reducing dark current within an image sensor includes applying, at a first time period, a first set of voltages to the phases of gate electrodes of vertical shift registers sufficient to accumulate holes of the vertical shift register, beneath each gate electrode and applying, at a second time period, a second voltage to a first set of the gate electrodes while simultaneously applying a more positive voltage to a second set of gate electrodes, the second voltage being of sufficient potential so holes that were accumulated beneath the second set of gate electrodes during the first time are collected and stored beneath the first set of gate electrodes during the second time period. Moreover, the method applies, at a third time period, a third voltage to the second set of gate electrodes while simultaneously applying a more positive voltage to the first set of gate electrodes, such that the previously accumulated holes beneath the first set of gate electrodes are transferred beneath the second set of gate electrodes; and returns the first and second sets of gate electrode voltages to their levels at the first time period.

Claims

1. A method for reducing dark current within an interline CCD image sensor comprising the steps of:

providing the interline CCD image sensor with a matrix of pixels arranged in a plurality of rows and columns with a vertical shift register allocated for each of the columns and at least one horizontal shift register operatively coupled to the vertical shift registers, wherein each of the columns of pixels are formed with the vertical shift registers having a plurality of phases allocated for each of the pixels and a plurality of gate electrodes of the vertical shift register for each of the pixels, and clocking means for causing the transfer of charge from the pixels to the vertical shift registers and through the horizontal shift register;

applying, at a first time period, a first set of voltages to the phases of the gate electrodes of the vertical shift registers sufficient to accumulate holes substantially at a surface of the image sensor in the vertical shift register, beneath each gate electrode;

applying, at a second time period, a second voltage to a first set of the gate electrodes while simultaneously applying a more positive voltage to a second set of gate electrodes, the second voltage being of sufficient potential so holes that were accumulated beneath the second set of gate electrodes during the first time are collected and stored beneath the first set of gate electrodes during the second time period;

applying, at a third time period, a third voltage to the second set of gate electrodes while simultaneously applying a more positive voltage to the first set of gate electrodes, such that the previously accumulated holes beneath the first set of gate electrodes are transferred beneath the second set of gate electrodes;

returning the first and second sets of gate electrode voltages to their levels at the first time period; and

applying an additional positive voltage pulse to a first set of gate electrodes during a period of more positive voltage.

2. The method of claim 1 further including the step of applying voltages to the first and second sets of gate electrodes between the third applying step and the returning step to cause excess charge to be returned under the preceding gate electrode.

3. The method of claim 1 wherein the vertical shift registers are two-phase devices and wherein the third voltage is at substantially the same voltage as the second voltage.

4. The method of claim 2 wherein the step of applying the first voltage to the phases of the vertical shift registers occurs during a readout period of the horizontal shift register.

5. The method of claim 1 wherein the image sensor is an interline transfer type image sensor.

6. The method of claim 1 further comprising the step of substantially simultaneously applying a negative pulse to the second set of gate electrodes while the additional positive voltage pulse is applied to the first set of gate electrodes during the period of more positive voltage.