Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks

• US 6,996,008 B2
• Filed: 05/06/2004
• Issued: 02/07/2006
• Est. Priority Date: 02/17/2000
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Conley, Kevin M., Mangan, John S., Craig, Jeffrey G.
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Nguyen, Tuan T.
• Application Number:
  US10/841,406
• Publication Number:
  US 20040210709A1
• Time in Patent Office: 642 Days
• Field of Search: 365/185.11, 365/189.04, 365/185.09
• US Class Current: 365/185.11
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/107 Programming all cells in an array, sector or block to the same state prior to flash erasing
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.

Claims

1. A method of operating a re-programmable non-volatile memory system having memory cells organized into distinct blocks of simultaneously erasable cells, wherein:

user data stored in individual ones of a group of a plurality of said blocks,

a plurality of records that individually contain data of characteristics of a different one of the group of blocks are stored without user data in at least one block not within said group of blocks, and

wherein the records individually contain a flag that indicates whether the one block of the first group is good or defective, and, if good, additionally contains data of operating parameters for the one block, and, if defective, additionally contains data of an address of another of the first group of blocks that is good.

2. The method of claim 1, wherein the operating parameters include at least one operating voltage for the one block.

3. The method of claim 1, wherein the operating parameters include a cumulative indication of a number of times the one block has been erased.

4. The method of claim 1, wherein the user are stored in individual ones of a group of a plurality of said blocks along with a redundancy code calculated from the user data.

5. The method of claim 1, wherein the user data are stored in individual ones of a group of a plurality of said blocks without data of characteristics of the memory cell blocks.

6. The method of claim 1, wherein the record contains either data of operating parameters for the one block or an address of a another of the first group of blocks in a common set of bits.

7. A method of operating re-programmable non-volatile memory system having memory cells organized into distinct blocks of memory cells that are simultaneously erasable, comprising;

storing user data in individual ones of a first group of a plurality of said blocks,

storing a plurality of records in a second group of at least one of said blocks that individually contains data characterizing a unique one of the first group of blocks, the second group of at least one of said blocks being absent of user data, and

wherein the data characterizing a unique one of the first group of blocks includes data of either a first or a second attribute of the one block that are stored in a common set of bits within the individual record.

8. The method of claim 7, wherein the first attribute includes operating parameters of the one block and the second attribute includes an address of another block.