Redundant memory structure using bad bit pointers
First Claim
1. A memory device comprising:
- a memory array;
a plurality of memory cells;
circuitry operative to;
detect an error in writing data in a memory cell of the memory array;
write a pointer in the plurality of memory cells, the pointer identifying which memory cell in the memory array contains the error;
read the data from the memory array;
read the pointer from the plurality of memory cells;
from the pointer, identify which memory cell in the memory array contains the error; and
correct the error.
5 Assignments
0 Petitions
Accused Products
Abstract
The preferred embodiments described herein relate to a redundant memory structure using bad bit pointers. In one preferred embodiment, data is written in a first plurality of memory cells, and an error is detected in writing data in one of the memory cells. In response to the detected error, a pointer is written in a second plurality of memory cells, the pointer identifying which memory cell in the first plurality of memory cells contains the error. During a read operation, the data is read from the first plurality of memory cells, and the pointer is read from the second plurality of memory cells. From the pointer, the memory cell containing the error is identified, and the error is corrected. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
-
Citations
33 Claims
-
1. A memory device comprising:
-
a memory array; a plurality of memory cells; circuitry operative to; detect an error in writing data in a memory cell of the memory array; write a pointer in the plurality of memory cells, the pointer identifying which memory cell in the memory array contains the error; read the data from the memory array; read the pointer from the plurality of memory cells; from the pointer, identify which memory cell in the memory array contains the error; and correct the error. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 31)
-
-
15. A memory device comprising:
-
a memory array comprising a plurality of sub-arrays, wherein at least one sub-array comprises a plurality of pointers identifying which memory cells in the memory array are bad and further identifying a respective plurality of correct bits for those bad memory cells; a content addressable memory array operative to compare an address with the identifying information stored in the plurality of pointers; and circuitry operative to, if the content addressable memory array determines a match exists between the address and the identifying information, replace the bit at the address with the correct bit specified in the pointer. - View Dependent Claims (16, 17, 18, 19, 20, 21, 32)
-
-
22. A memory device comprising:
-
a memory array comprising a plurality of primary rows of memory cells and a plurality of redundant rows of memory cells; a leakage current detector operative to detect an error in a primary row of the memory array; and circuitry operative to replace a primary row of memory cells with a redundant row of memory cells in response to the leakage current detector detecting an error in the primary row of memory cells. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 33)
-
Specification