Semiconductor memory device

• US 6,996,020 B2
• Filed: 11/25/2003
• Issued: 02/07/2006
• Est. Priority Date: 12/17/2002
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Yoshida, Katsuya
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US10/720,080
• Publication Number:
  US 20040114424A1
• Time in Patent Office: 805 Days
• Field of Search: 365/210, 365/230.03, 365/233, 365/190
• US Class Current: 365/210.1
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/025 in signal lines

Abstract

A plurality of dummy bit lines are disposed together with a plurality of bit line pairs in a memory cell array. In selectively driving a memory cell connected to the bit line pair, a timing control circuit controls the timing of the driving operation, based on signal change in the plural dummy bit lines, thereby detecting the influences of the process variation in a plurality of positions in the memory cell array. Thus, the influence of the process variation given to the operation of a semiconductor memory device can be further alleviated, compared with the case when one dummy bit line is used.

Claims

1. A semiconductor memory device selectively driving memory cells in accordance with an input signal inputted from an external part to output data or to input and output data, said semiconductor memory device comprising:

a memory cell array having a plurality of dummy bit line pairs and a plurality of bit line pairs adjacently disposed to each other, dummy memory cells being connected to said dummy bit line pairs respectively, and memory cells being connected to said bit line pairs respectively; and

a timing control circuit controlling a timing of a driving operation based on signals supplied via said dummy bit line pairs, when selectively driving the memory cell connected to said bit line pair.

2. The semiconductor memory device according to claim 1, wherein, in said memory cell array, said dummy bit line pairs are adjacently disposed at positions closer to said timing control circuit than an arbitrary one of said bit line pairs.

3. The semiconductor memory device according to claim 1, wherein, in said memory cell array, said dummy bit line pairs are adjacently disposed at positions more distant from said timing control circuit than an arbitrary one of said bit line pairs.

4. The semiconductor memory device according to claim 1, wherein, in said memory cell array, said dummy bit line pairs are adjacently disposed and said bit line pairs are disposed on both sides of said dummy bit line pairs adjacently disposed.

5. The semiconductor memory device according to claim 1, wherein, in said memory cell array, said dummy bit line pairs are divided into two sets, and the dummy bit line pairs in one of the sets are adjacently disposed at a position closer to said timing control circuit than an arbitrary one of the bit line pairs and the dummy bit line pairs in the other set are adjacently disposed at a position more distant from said timing control circuit than an arbitrary one of the bit line pairs.

6. The semiconductor memory device according to claim 5, wherein said dummy bit line pairs are divided into two sets, one set consisting of N pieces (N is a natural number) of the dummy bit line pairs and the other set consisting of N pieces or (N+1) pieces of the dummy bit line pairs.

7. The semiconductor memory device according to claim 1, wherein, in said memory cell array, said dummy bit line pairs are disposed at a predetermined pitch.

8. The semiconductor memory device according to claim 1, wherein, in said memory cell array, said dummy bit line pairs are divided into a plurality of sets each consisting of a substantially equal number of dummy bit line pairs, the dummy bit line pairs in each of the sets being adjacently disposed, and the plural sets of the dummy bit line pairs being disposed at a predetermined pitch.

9. The semiconductor memory device according to claim 1, wherein said memory cell array is provided in plurality.

10. The semiconductor memory device according to claim 1, wherein said dummy bit line pairs are connected in series.

11. The semiconductor memory device according to claim 10, wherein said timing control circuit generates a timing generating signal based on the signals supplied via said dummy bit line pairs and controls the timing of the driving operation based on the generated timing generating signal.

12. The semiconductor memory device according to claim 1, wherein said timing control circuit controls the timing of the driving operation based on a signal supplied via a dummy bit line of said dummy bit line pairs with the slowest signal change among said dummy bit line pairs.

13. The semiconductor memory device according to claim 1, wherein said timing control circuit has a logical arithmetic circuit having an input terminal to which one end of each dummy bit line of said dummy bit line pairs are connected, and said logical arithmetic circuit inverts a signal level of an output signal in accordance with a change in the signals supplied via said dummy bit lines of said dummy bit line pairs.

14. The semiconductor memory device according to claim 1, wherein said timing control circuit controls the timing of the driving operation based on a potential difference between a potential of at least one dummy bit line of each of said dummy bit line pairs and a reference potential.

15. The semiconductor memory device according to claim 1, wherein each of said dummy memory cells and said memory cells has two inverter circuits, said two inverter circuits have input terminals and output terminals mutually cross-coupled, and the input terminals of the two inverter circuits in each of the dummy memory cells are further connected to power sources supplying predetermined voltages.

16. The semiconductor memory device according to claim 1, wherein each of the dummy memory cells and the memory cells has two inverter circuits, the two inverter circuits in each of the memory cells have input terminals and output terminals mutually cross-coupled, and the two inverter circuits in each of the dummy memory cells have input terminals connected to power sources supplying predetermined voltages respectively and output terminals connected to different dummy bit lines of said dummy bit line pairs respectively.

17. The semiconductor memory device according to claim 1, wherein a predetermined number of dummy memory cells are selectively driven among said dummy memory cells connected to said dummy bit line pairs respectively, the dummy memory cells being selected in descending order of a distance in said dummy bit line pairs from said timing control circuit.

18. The semiconductor memory device according to claim 1, wherein said timing control circuit controls the timing of the driving operation based on a signal supplied via at least one dummy bit line of said dummy bit line pairs.

19. The semiconductor memory device according to claim 1, wherein said memory cell array has a dummy word line for selectively driving a dummy memory cell connected to said dummy bit line pairs and a word line for selectively driving a memory cell connected to said bit line pairs.