Boosted voltage generating circuit and semiconductor memory device having the same

• US 6,996,024 B2
• Filed: 06/14/2004
• Issued: 02/07/2006
• Est. Priority Date: 05/25/2000
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tanzawa, Toru, Miyaba, Takeshi, Atsumi, Shigeru
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US10/866,131
• Publication Number:
  US 20040240271A1
• Time in Patent Office: 603 Days
• Field of Search: 365/226, 365/189.09, 365/189.11, 365/185.18
• US Class Current: 365/226
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.

Claims

1. A semiconductor memory device comprising:

a memory cell array including a plurality of data-erasable memory cells including drain and source regions formed in a semiconductor region and gate electrodes, for storing data;

a first voltage output circuit supplied with a first voltage, for outputting a second voltage obtained by boosting the first voltage;

a second voltage output circuit coupled with the first voltage output circuit, for generating a third voltage whose voltage value is smaller than a value of the second voltage at a data program time;

a row decoder circuit coupled with the second voltage output circuit, for supplying the third voltage to a selected one of the gate electrodes at a data program time; and

a first switch circuit coupled with the first voltage output circuit, for supplying the second voltage to at least one of the source regions at a data erase time.

2. The semiconductor memory device according to claim 1, wherein the second voltage output circuit generates a fourth voltage whose voltage value is smaller than a value of the third voltage at a program verify time.

3. The semiconductor memory device according to claim 1, wherein the second voltage output circuit generates a fourth voltage whose voltage value is smaller than a value of the third voltage at an erase verify time.

4. The semiconductor memory device according to claim 1, wherein the second voltage output circuit generates a fourth voltage whose voltage value is smaller than a value of the third voltage at a weak program time.

5. The semiconductor memory device according to claim 1 further comprising:

a second switch circuit coupled with a fourth voltage node and an output node of the third voltage, for supplying the fourth voltage to the output node of the third voltage at a data readout time.