Walsh-Hadamard decoder

• US 6,996,163 B2
• Filed: 03/27/2003
• Issued: 02/07/2006
• Est. Priority Date: 03/27/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: ArrayComm LLC (Ygomi LLC)
• Inventors: Bhora, Veerendra, Roy, Pulakesh, Boros, Tibor
• Primary Examiner(s): PHU, PHUONG M
• Application Number:
  US10/402,039
• Publication Number:
  US 20040190604A1
• Time in Patent Office: 1,048 Days
• Field of Search: 375140-142, 375/147, 375/150, 375/259, 375/316, 708/410, 708/400
• US Class Current: 375/150
• CPC Class Codes: H04B 1/7093 Matched filter type
• CPC Class Codes: H04B 2001/70935 using a bank of matched fileters, e.g. Fast Hadamard Transform

Abstract

In one embodiment, a Walsh-Hadamard decoder can have a hardware efficient Fast Hadamard Transform (“FHT”) engine. In one embodiment, the FHT engine can include an input to receive an input sequence to be decoded into a Walsh-Hadamard codeword. The FHT engine can further include a controller to correlate the received input sequence with a plurality of Walsh-Hadamard codewords using two add/subtract modules. In one embodiment, the two add/subtract modules operate in parallel.

Claims

1. A Fast Hadamard Transform (“

FHT”

) engine comprising;

a controller to generate a phase-select signal, the phase select signal indicating whether the FHT engine is in a partitioning phase or a processing phase;

a first memory;

a second memory;

a first add/subtract module configured to receive an input sequence representing a signal, and to output intermediate values to the first memory and the second memory in response to the phase-select signal indicating the partitioning phase;

wherein the first add/subtract module is configured receive intermediate values stored in the first memory, and to replace the received intermediate values in the first memory with the output of the first add/subtract module in response to the phase-select signal indicating the processing phase.

2. The FHT engine of claim 1, further comprising a second add/subtract module configured to receive intermediate values stored in the second memory, and to replace the received intermediate values in the second memory with the output of the second add/subtract module in response to the phase-select signal indicating the processing phase.

3. The FHT engine of claim 2, wherein the controller further generates a first and second memory address signal,.the first and second memory address identifying the two intermediate values in both the first and second memories that are to be replaced using the first and second add/subtract modules respectively.

4. The FHT engine of claim 1, wherein the first memory and the second memory each comprise a dual-port random access memory (RAM).