Apparatus for providing packets in a peripheral interface circuit of an I/O node of a computer system
First Claim
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1. An apparatus for providing packets in a peripheral interface circuit, said apparatus comprising:
- a buffer configured to accumulate data received on a first bus; and
a control unit coupled to said buffer and configured to transmit a data packet containing a first number of bytes of said data in response to detecting that any of said bytes of said data is invalid;
wherein said control unit is further configured to transmit said data packet containing a second number of bytes of said data in response to detecting that all of said bytes are valid.
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Abstract
An apparatus for providing packets in a peripheral interface circuit of an I/O node of a computer system. The apparatus includes a buffer that may be configured to accumulate data received on a first bus. The apparatus further includes a control unit coupled to the buffer which may be configured to transmit a data packet containing a first number of bytes of the data in response to detecting that any of the bytes of the data is invalid. The control unit may be further configured to transmit the data packet containing a second number of bytes of the data in response to detecting that all of the bytes are valid.
35 Citations
28 Claims
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1. An apparatus for providing packets in a peripheral interface circuit, said apparatus comprising:
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a buffer configured to accumulate data received on a first bus; and a control unit coupled to said buffer and configured to transmit a data packet containing a first number of bytes of said data in response to detecting that any of said bytes of said data is invalid; wherein said control unit is further configured to transmit said data packet containing a second number of bytes of said data in response to detecting that all of said bytes are valid. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for providing packets in a peripheral interface circuit, said method comprising:
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accumulating data received on a first bus; detecting whether any of said accumulated data is invalid; transmitting a data packet containing a first number of bytes of said data in response to detecting that any of said bytes of said data is invalid; and transmitting said data packet containing a second number of bytes of said data in response to detecting that all of said bytes are valid. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A computer system comprising:
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a processor; one or more input/output nodes each including a peripheral interface circuit including an apparatus comprising; a buffer configured to accumulate data received on a first bus; and a control unit coupled to said buffer and configured to transmit a data packet containing a first number of bytes of said data in response to detecting that any of said bytes of said data is invalid; wherein said control unit is further configured to transmit said data packet containing a second number of bytes of said data in response to detecting that all of said bytes are valid. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28)
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Specification