Methods and apparatus for computer bus error termination

• US 6,996,750 B2
• Filed: 05/31/2001
• Issued: 02/07/2006
• Est. Priority Date: 05/31/2001
• Status: Expired due to Term

• Current Assignee: Stratus Technologies Ireland Ltd. (Stratus Technologies Bermuda Holdings Ltd.)
• Original Assignee: Stratus Technologies Bermuda Ltd. (Stratus Technologies Bermuda Holdings Ltd.)
• Inventors: Tetreault, Mark
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): MASKULINSKI, MICHAEL C
• Application Number:
  US09/871,180
• Publication Number:
  US 20020194548A1
• Time in Patent Office: 1,713 Days
• Field of Search: 714/44, 714/43
• US Class Current: 714/44
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/3027 where the computing system component is a bus
• CPC Class Codes: G06F 11/3055 Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction by redundancy in operation G06F11/14; error detection or correction by redundancy in hardware G06F11/16

Abstract

In a computer system having a bus architecture, a system and process for isolating a device from a bus without interrupting system operation is described, the system including bus interface logic monitoring and reporting activity on the bus, isolation control logic receiving error signals from error detectors, and isolation switches through which devices are interconnected to the bus, the isolation switches allowing for the isolation of the devices from the bus. The isolation control logic determines the devices to be isolated responsive to the reported error and, in turn, transmits an isolation switch control signal to the isolation switch(es) associated with the identified device(s) to isolate those device(s) from the bus. In some embodiments, errors are reported by system software, input/output virtual address error detectors for systems using virtual memory addressing, protocol error detectors, and sensors sensing the physical removal of a bus-connected device from its bus interface slot.

Claims

1. An apparatus for isolating, in response to a device isolation signal and a bus idle status signal, a device from a bus without interrupting system operation, the apparatus comprising:

bus interface logic in communication with the bus, the bus interface logic generating a signal indicating the idle status of the bus;

an isolation switch in communication with the bus;

protocol checker logic configured to monitor the validity of bus transactions and to generate a device isolation control signal on a device isolation control line; and

isolation control logic in communication with the bus interface logic, the device isolation control line, and the isolation switch,

wherein the isolation control logic transmits an isolation switch control signal to the isolation switch in response to the generated bus idle status signal from the bus interface logic and the received device isolation signal on the device isolation control line.

2. The apparatus of claim 1 wherein the bus interface logic comprises a state machine.

3. The apparatus of claim 1 wherein the bus interface logic comprises combinatorial logic.

4. The apparatus of claim 1 wherein the bus interface logic monitors all bus transactions.

5. The apparatus of claim 1 wherein the bus idle status signal generated by the bus interface logic indicates that the bus is idle.

6. The apparatus of claim 1 wherein the isolation control logic comprises combinatorial logic.

7. The apparatus of claim 1 wherein the isolation control logic receives the device isolation signal on the device isolation control line from logic monitoring the operational status of the system.

8. The apparatus of claim 1 wherein the isolation control logic receives the device isolation signal on the device isolation control line from a hot-plug logic element.

9. The apparatus of claim 8 wherein the hot-plug logic element generates the device isolation signal on the device isolation control line responsive to the physical removal of the device from its slot.

10. The apparatus of claim 1 wherein the device is isolated from the bus at substantially the same time that the protocol violation was detected.

11. The apparatus of claim 10 wherein the protocol checker logic generates the device isolation signal on the device isolation control line responsive to a detected protocol violation.

12. The apparatus of claim 1 wherein the bus transactions are communicated on the bus in relation to clock cycles, and wherein the device is isolated from the bus within one clock cycle of the detected protocol violation.

13. The apparatus of claim 12 wherein the protocol checker logic generates the device isolation signal on the device isolation control line during the same clock cycle as the detected protocol violation.

14. The apparatus of claim 1 wherein the isolation control logic comprises a timer measuring elapsed time.

15. The apparatus of claim 14 wherein the timer measures elapsed time relative to a system event.

16. The apparatus of claim 15 wherein a timeout signal is generated in response to the elapsed time exceeding a predetermined threshold.

17. The apparatus of claim 16 wherein the isolation control logic transmits a bus reset signal responsive to receiving both the device isolation signal on the device isolation control line and the timeout signal from the timer.

18. In a system having a bus controlled by a bus controller, a device isolation control line, and having at least one bus device in communication with the bus via an isolation switch, a method for isolating the bus device from the bus, the method comprising the steps:

(a) detecting a protocol violation on the bus and generating an isolation control signal on a device isolation control line in response to the detected protocol violation;

(b) receiving the isolation control signal on the device isolation control line, the signal identifying a bus device to be isolated, the bus device performing a bus transaction;

(c) receiving a bus idle status signal;

(d) transmitting an isolation switch control signal responsive to both the received device isolation signal and the received bus idle status signal; and

(e) isolating the device from the bus.

19. The method of claim 18 further comprising the step of isolating the identified bus device from the bus responsive to the received bus device isolation signal.

20. The method of claim 18 further comprising the step of inhibiting bus access.

21. The method of claim 18 further comprising the steps of:

receiving a timeout signal; and

resetting the bus responsive to receiving both the timeout signal and the bus status idle signal indicating that the bus is not idle.

22. The method of claim 18 wherein the device is isolated from the bus at substantially the same time that the protocol violation was detected.

23. An apparatus for isolating a device from a bus without interrupting system operation, the apparatus comprising:

means for receiving a signal identifying a bus device to be isolated, the identified bus device performing a bus transaction;

means for receiving a bus idle status signal;

means for detecting a protocol violation on the bus and sending an isolation control signal to the means for receiving a signal identifying a bus device to be isolated in response to the detected protocol violation; and

means for transmitting an isolation switch control signal responsive to both the received bus device isolation signal and the received bus idle status signal.