Automatic code generation for integrated circuit design

• US 6,996,799 B1
• Filed: 08/08/2000
• Issued: 02/07/2006
• Est. Priority Date: 08/08/2000
• Status: Expired due to Term

• Current Assignee: Geo Semiconductor Incorporated
• Original Assignee: Mobilygen Corporation (Analog Devices, Inc.)
• Inventors: Monsen, Kristan J., Cismas, Sorin C., So, Henry K.
• Primary Examiner(s): Chaki, Kakali
• Assistant Examiner(s): Wood, William H.
• Application Number:
  US09/634,131
• Time in Patent Office: 2,009 Days
• Field of Search: 717104-109, 717/121, 717124-135, 717/120, 717/136, 716 2- 4, 716/1, 716/18, 716/5, 716/7, 716/12, 716/13, 703 13- 14, 703/22
• US Class Current: 717/106
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

An integrated circuit is designed by interconnecting pre-designed data-driven cores (intellectual property, functional blocks). Hardware description language (e.g. Verilog or VHDL) and software language (e.g. C or C++) code for interconnecting the cores is automatically generated by software tools from a central circuit specification. The central specification recites pre-designed hardware cores (intellectual property) and the interconnections between the cores. HDL and software language test benches, and timing constraints are also automatically generated from the central specification. The automatic generation of code simplifies the interconnection of pre-existing cores for the design of complex integrated circuits.

Claims

1. A computer-implemented method of designing an integrated circuit, comprising the steps of:

a) establishing a central specification for the integrated circuit, the central specification designating a plurality of cores and a plurality of interconnections between the cores;

b) establishing a set of software lance models for the cores, each software language model implementing an internal algorithm of one of the cores;

c) establishing a set of hardware description language models for the cores, each hardware description language model implementing an internal logic of one of the cores;

d) generating software language core interconnection code for interconnecting the software language models according to the central specification, to generate a software language model of the circuit; and

e) generating hardware description language core interconnection code for interconnecting the hardware description language models according to the central specification, to generate a hardware description language model of the circuit.

2. The method of claim 1 wherein:

a) the central specification designates a set of input tokens and a set of output tokens for each core; and

b) the central specification designates a set of token fields for each interconnection.

3. The method of claim 2 wherein generating the hardware description language core interconnection code comprises generating a set of port declarations from the sets of token fields, input tokens, and output tokens defined in the central specification.

4. The method of claim 2 wherein generating the hardware description language core interconnection code comprises generating an interface port list from the sets of token fields, input tokens, and output tokens defined in the central specification.

5. The method of claim 2 wherein generating the hardware description language core interconnection code comprises generating a set of data type declarations from the sets of token fields, input tokens, and output tokens defined in the central specification.

6. The method of claim 2 wherein generating the hardware description language core interconnection code comprises generating a set of bus definitions from the sets of token fields, input tokens, and output tokens defined in the central specification.

7. The method of claim 2 wherein:

a) at least one of the token fields defined in the specification includes a token field parameter; and

b) the central specification further comprises an assignment of a value for the token field parameter.

8. The method of claim 1 further comprising generating a hardware description language declaration for a clock input port and a reset input port for each of the cores.

9. The method of claim 1 wherein, for each core:

a) the central specification defines a set of core parameters; and

b) generating the hardware description language model comprises generating a set of hardware description language parameter declarations from the set of core parameters.

10. The method of claim 1 wherein:

a) for each core, the central specification defines a set of input tokens and a set of output tokens; and

b) generating the software language model comprises generating declarations for a set of pipes and a set of tokens from the sets of input tokens and output tokens defined in the central specification, each pipe serving to transfer tokens between the cores.

11. The method of claim 1 further comprising the step of generating a test bench for the integrated circuit, the test bench including the hardware description language model and the software language model, for comparing a result of a software simulation of the circuit to a result of a hardware simulation of the circuit.

12. The method of claim 11 wherein the test bench comprises a bus driver module for driving the hardware description language model of the integrated circuit.

13. The method of claim 11 wherein the test bench further comprises a software-driver module for driving the software language model of the integrated circuit.

14. The method of claim 11 wherein the test bench further comprises a monitor module for comparing the result of the software simulation to the result of the hardware simulation.

15. The method of claim 11 wherein the test bench further comprises a bus receiver module for requesting tokens from the hardware description language model.

16. The method of claim 1, further comprising the steps of:

a) driving the hardware description language model with a simulation hardware input;

b) driving the software language model with a simulation software input;

c) detecting a response of the hardware description language model to the simulation hardware input;

d) detecting a response of the software language model to the simulation software input; and

e) comparing the response of the hardware description language model to the simulation hardware input to the response of the software language model to the simulation software input.

17. The method of claim 16 wherein steps (b) and (e) are performed at least in part concurrently with a simulation of the hardware description language model.

18. The method of claim 1 further comprising the step of generating a synthesis constraint for the circuit.

19. The method of claim 18 wherein the synthesis constraint limits the fraction of a clock cycle used by a core interface.

20. The method of claim 1 wherein generating the hardware description language model comprises the step of instantiating a hardware subcore model forming part of one of the cores.

21. The method of claim 20 wherein generating the software language model comprises the step of instantiating a software subcore model forming part of one of the cores.

22. The method of claim 1 wherein generating the software language model comprises the step of instantiating a software subcore model forming part of one of the cores.

23. The method of claim 1 wherein the plurality of interconnections comprises a dedicated interconnection connecting a first core and a second core, the first interconnection comprising:

a) a ready connection for carrying a ready signal from the first core to the second core, the ready signal being indicative of a readiness of the first core to transmit a token to the second core;

b) a request connection for carrying a request signal from the second core to the first core, the request signal being indicative of a readiness of the second core to receive the token from the first core; and

c) a token bus for transmitting the token from the first core to the second core upon a synchronous assertion of the ready signal and the request signal.

24. The method of claim 1, wherein each of the plurality of cores is a data-driven core.

25. The method of claim 1, wherein the hardware description language core interconnection code designates a set of intercore handshake connections and a set of corresponding intercore data connections.

26. A computer-implemented method of designing an integrated circuit, comprising the steps of:

a) establishing a central specification for the integrated circuit, the central specification designating a plurality of cores and a plurality of interconnections between the cores;

b) for each core, establishing hardware description language template code for an internal logic of the core;

c) for each core, establishing software language template code for an internal algorithmic functionality of the core;

d) processing the central specification to generate software language core interconnection code for interconnecting the software language template code for the cores, to generate a software language model of the circuit; and

e) processing the central specification to generate hardware description language core interconnection code for interconnecting the hardware description language template code for the cores, to generate a hardware description language model of the circuit.

27. The method of claim 26 wherein the hardware description language core interconnection code comprises an interface port list, a set of port declarations, a set of interface bus definitions, and a set of data type declarations.

28. The method of claim 27 wherein the port list comprises a global clock port and a reset port for each core.

29. The method of claim 26 wherein the software language core interconnection code comprises a set of pipe declarations and a set of token declarations.

30. The method of claim 26, further comprising the step of processing the central specification to add a parameter list to the hardware description language template code.

31. The method of claim 26, further comprising the step of processing the central specification to add a parameter list to the software language template code.

32. The method of claim 26, wherein each of the plurality of cores is a data-driven core.

33. The method of claim 26, wherein the hardware description language core interconnection code designates a set of intercore handshake connections and a set of corresponding intercore data connections.

34. A computer-implemented method of designing an integrated circuit, comprising the steps of:

a) establishing a central specification for the integrated circuit, the central specification designating a plurality of cores and a plurality of dedicated interconnections between the cores;

b) generating a software language, functional model of the integrated circuit from the central specification and from a set of software language, functional models of the cores;

c) generating a hardware description language model of the integrated circuit from the central specification and from a set of hardware description language models of the cores, the hardware description language model of the integrated circuit designating a set of intercore handshake connections and a set of corresponding intercore data connections;

d) generating a test bench for the circuit from the hardware description language model and the software language model, for comparing a result of a software simulation of the circuit to a result of a hardware simulation of the circuit; and

e) generating a set of logic synthesis constraints for the circuit from the central specification, for constraining a logic synthesis of the circuit.

35. The method of claim 34, wherein each of the plurality of cores is a data-driven core.

36. The method of claim 34, wherein the hardware description language core interconnection code designates a set of intercore handshake connections and a set of corresponding intercore data connections.

37. A computer-implemented method of designing an integrated circuit, comprising the steps of:

a) establishing a central specification for the integrated circuit, the central specification designating a plurality of cores and a plurality of interconnections between the cores;

b) generating a software language, functional model of the integrated circuit from the central specification and from a set of software language, functional models of the cores; and

c) generating a hardware description language model of the integrated circuit from the central specification and from a set of hardware description language models of the cores.

38. The method of claim 37, wherein each of the plurality of cores is a data-driven core.

39. The method of claim 37, wherein the hardware description language core interconnection code designates a set of intercore handshake connections and a set of corresponding intercore data connections.

40. A computer system programmed to perform the steps of:

a) establishing a central specification for the integrated circuit, the central specification designating a plurality of cores and a plurality of interconnections between the cores;

b) generating a software language, functional model of the integrated circuit from the central specification and from a set of software language, functional models of the cores; and

c) generating a hardware description language model of the integrated circuit from the central specification and from a set of hardware description language models of the cores.

41. The system of claim 40, wherein each of the plurality of cores is a data-driven core.

42. The system of claim 40, wherein the hardware description language core interconnection code designates a set of intercore handshake connections and a set of corresponding intercore data connections.

43. A computer-readable medium encoding instructions to perform the steps of:

a) establishing a central specification for the integrated circuit, the central specification designating a plurality of cores and a plurality of interconnections between the cores;

b) generating a software language, functional model of the integrated circuit from the central specification and from a set of software language, functional models of the cores; and

c) generating a hardware description language model of the integrated circuit from the central specification and from a set of hardware description language models of the cores.

44. The computer readable medium of claim 43, wherein each of the plurality of cores is a data-driven core.

45. The computer readable medium of claim 43, wherein the hardware description language core interconnection code designates a set of intercore handshake connections and a set of corresponding intercore data connections.

46. A circuit design apparatus comprising:

a) a storage device for establishing a central specification for the integrated circuit, the central specification designating a plurality of cores and a plurality of interconnections between the cores;

b) software interconnection means for generating a software language, functional model of the integrated circuit from the central specification and from a set of software language, functional models of the cores; and

c) hardware description language interconnection means for generating a hardware description language model of the integrated circuit from the central specification and from a set of hardware description language models of the cores.

47. The apparatus of claim 46, wherein each of the plurality of cores is a data-driven core.

48. The apparatus of claim 46, wherein the hardware description language core interconnection code designates a set of intercore handshake connections and a set of corresponding intercore data connections.