Software implementation of synchronous memory barriers
First Claim
1. A method for selectively emulating sequential consistency in software comprising:
- (a) forcing each CPU to execute a memory barrier instruction; and
(b) having each CPU send an indicator communicating completion of said memory barrier instruction.
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Abstract
Selectively emulating sequential consistency in software improves efficiency in a multiprocessing computing environment. A writing CPU uses a high priority inter-processor interrupt to force each CPU in the system to execute a memory barrier. This step invalidates old data in the system. Each CPU that has executed a memory barrier instruction registers completion and sends an indicator to a memory location to indicate completion of the memory barrier instruction. Prior to updating the data, the writing CPU must check the register to ensure completion of the memory barrier execution by each CPU. The register may be in the form of an array, a bitmask, or a combining tree, or a comparable structure. This step ensures that all invalidates are removed from the system and that deadlock between two competing CPUs is avoided. Following validation that each CPU has executed the memory barrier instruction, the writing CPU may update the pointer to the data structure.
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Citations
28 Claims
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1. A method for selectively emulating sequential consistency in software comprising:
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(a) forcing each CPU to execute a memory barrier instruction; and
(b) having each CPU send an indicator communicating completion of said memory barrier instruction. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A computer system, comprising:
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multiple processors;
an instruction for forcing each CPU to execute a memory barrier instruction; and
an instruction manager for indicating completion of said memory barrier instruction. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. An article comprising:
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a computer-readable medium;
means in the medium for forcing each CPU to execute a memory barrier instruction; and
an instruction manager for indicating completion of said memory barrier instruction. - View Dependent Claims (22, 23, 24, 25, 26)
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27. A method for selectively emulating sequential consistency in software comprising:
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(a) forcing each CPU to execute a memory barrier instruction;
(b) having each CPU send an indicator communicating completion of said memory barrier instruction;
(c) satisfying groups of concurrent memory barrier execution requests with a single set of memory barrier instruction executions; and
(d) wherein the step of forcing each CPU to execute a memory barrier instruction includes sending an interprocessor interrupt to all CPUs forcing execution of said memory barrier instruction. - View Dependent Claims (28)
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Specification