Method for manufacturing a silicon sensor and a silicon sensor

• US 6,998,059 B2
• Filed: 03/21/2002
• Issued: 02/14/2006
• Est. Priority Date: 03/21/2001
• Status: Expired due to Term

• Current Assignee: Murata Manufacturing Co Limited
• Original Assignee: VTI Technologies Oy (Murata Manufacturing Co Limited)
• Inventors: Kuisma, Heikki, Lahdenperä, Juha, Mutikainen, Risto
• Primary Examiner(s): KWOK, HELEN C
• Application Number:
  US10/472,465
• Publication Number:
  US 20040074301A1
• Time in Patent Office: 1,426 Days
• Field of Search: 438 52- 53, 438/702, 438/738, 438/748, 216/2, 216/11, 216/48, 216/83, 216/96
• US Class Current: 216/2
• CPC Class Codes: B81B 2201/0235 Accelerometers
• CPC Class Codes: B81C 1/00182 Arrangements of deformable or non-deformable structures, e.g. membrane and cavity for use in a transducer
• CPC Class Codes: B81C 2201/0132 Dry etching, i.e. plasma etching, barrel etching, reactive ion etching [RIE], sputter etching or ion milling
• CPC Class Codes: B81C 2201/0133 Wet etching
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 2015/0817 for pivoting movement of the mass, e.g. in-plane pendulum

Abstract

The invention relates to a method for manufacturing a silicon sensor structure and a silicon sensor. According to the method, into a single-crystal silicon wafer (10) is formed by etched opening at least one spring element configuration (7) and at least one seismic mass (8) connected to said spring element configuration (7). According to the invention, the openings and trenches (8) extending through the depth of the silicon wafer are fabricated by dry etch methods, and the etch process used for controlling the spring constant of the spring element configuration (7) is based on wet etch methods.

Claims

1. A method for manufacturing a silicon sensor structure, the method comprising the steps of:

forming by etched openings into a single crystal silicon wafer at least one spring element configuration and at least one seismic mass (8) connected to said spring element configuration,

fabricating openings and trenches extending through a depth an entire thickness of the silicon wafer by dry etch methods, and

basing an etch process used for controlling the spring constant of the spring element configuration on anisotropic wet etch methods after said fabricating step.

2. The method of claim 1, wherein an angle α

between a longitudinal axis of the spring element configuration and an equivalent crystal orientation in the plane of the silicon wafer selected to be greater than 15°

.

3. The method of claim 1, wherein a ratio L1/L between a length L of the spring element configuration to a longitudinal dimension L1 thereof in the direction of the crystal plane is selected to be smaller than 0.45.

4. The method of claim 1, wherein the wet etch method is carried out using alkaline etch processes that are anisotropic in regard to different crystal orientations.

5. The method of claim 1, wherein the etching of structures in orientations other than those perpendicular to a wafer plane is limited by making into the wafer such vertical trenches that are aligned substantially in different orientations than the orientation of the silicon wafer and are protected at sidewalls of the trenches against etch attack.

6. The method of claim 3, wherein both the dry etch method and the wet etch method are anisotropic.

7. The method of claim 2, wherein a ratio L1/L between a length L of the spring element configuration to a longitudinal dimension L1 thereof in the direction of the crystal plane is selected to be smaller than 0.45.

8. The method of claim 2, wherein the wet etch method is carried out using alkaline etch processes that are anisotropic in regard to different crystal orientations.

9. The method of claim 3, wherein the wet etch method is carried out using alkaline etch processes that are anisotropic in regard to different crystal orientations.

10. The method of claim 2, wherein the etching of structures in orientations other than those perpendicular to a wafer plane is limited by making into the wafer such vertical trenches that are aligned substantially in different orientations than the orientation of the silicon wafer and are protected at sidewalls of the trenches against etch attack.

11. The method of claim 3, wherein the etching of structures in orientations other than those perpendicular to a wafer plane is limited by making into the wafer such vertical trenches that are aligned substantially in different orientations than the orientation of the silicon wafer and are protected at sidewalls of the trenches against etch attack.

12. The method of claim 4, wherein the etching of structures in orientations other than those perpendicular to a wafer plane is limited by making into the wafer such vertical trenches that are aligned substantially in different orientations than the orientation of the silicon wafer and are protected at sidewalls of the trenches against etch attack.

13. The method of claim 2, wherein the equivalent crystal orientation is selected to be between 25°

and 65°

.

14. The method of claim 13, wherein the equivalent crystal orientation is about 45°

.

15. The method of claim 1, wherein said dry etch method includes no etch stop.