Methods of fabricating high voltage, high temperature capacitor and interconnection structures

• US 6,998,322 B2
• Filed: 03/06/2003
• Issued: 02/14/2006
• Est. Priority Date: 08/28/1998
• Status: Expired due to Term

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Das, Mrinal Kanti, Hagleitner, Helmut, Sheppard, Scott, Palmour, John W., Lipkin, Lori A.
• Primary Examiner(s): Thompson, Craig A.
• Assistant Examiner(s): Dolan, Jennifer M
• Application Number:
  US10/382,826
• Publication Number:
  US 20030160274A1
• Time in Patent Office: 1,076 Days
• Field of Search: 438/239, 438/240, 438/250, 438/253, 438/281, 438/393, 438/396, 438/597, 438/618, 438/622, 438/624, 438/634, 438/680, 257/296, 257/303, 257/306, 257/310, 257/774
• US Class Current: 438/393
• CPC Class Codes: H01G 4/1272 Semiconductive ceramic capacitors
• CPC Class Codes: H01G 4/20 using combinations of dielectrics from more than one of groups H01G4/02 - H01G4/06 H01G4/12 takes precedence
• CPC Class Codes: H01G 4/33 Thin- or thick-film capacitors thin- or thick-film circuits H01L27/00; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor H01L28/40
• CPC Class Codes: H01L 21/045 passivating silicon carbide surfaces
• CPC Class Codes: H01L 21/049 Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/6606 the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS

Abstract

Capacitors and interconnection structures for silicon carbide are provided having an oxide layer, a layer of dielectric material and a second oxide layer on the layer of dielectric material. The thickness of the oxide layers may be from about 0.5 to about 33 percent of the thickness of the oxide layers and the layer of dielectric material. Capacitors and interconnection structures for silicon carbide having silicon oxynitride layer as a dielectric structure are also provided. Such a dielectric structure may be between metal layers to provide a metal-insulator-metal capacitor or may be used as a inter-metal dielectric of an interconnect structure so as to provide devices and structures having improved mean time to failure. Methods of fabricating such capacitors and structures are also provided.

Claims

1. A method of fabricating a capacitor, comprising:

depositing a first oxide layer directly on a first metal layer so as to provide a first oxide layer having a first thickness;

depositing a layer of dielectric material on the first oxide layer to provide a high dielectric layer having a second thickness, the layer of dielectric material having a dielectric constant higher than the dielectric constant of the first oxide layer;

depositing a second oxide layer on the layer of dielectric material opposite the first oxide layer to provide a second oxide layer having a third thickness;

forming a second metal layer directly on the second oxide layer; and

wherein the first thickness are an order of magnitude smaller than the second thickness.

2. The method of claim 1, wherein the first oxide layer and the second oxide layer comprise silicon dioxide layers and wherein the layer of dielectric material comprises a silicon nitride layer.

3. The method of claim 1, wherein the first thickness is from about 10 to about 30 nm, the second thickness is from about 200 to about 300 nm and the third thickness is from about 10 to about 30 nm.

4. The method of claim 1, wherein the first and second metal layers comprise at least one of titanium, platinum, chromium and gold.

5. A method of fabricating an interconnection structure for an integrated circuit, comprising:

forming a plurality of semiconductor devices in a substrate;

forming an insulating layer on the plurality of semiconductor devices;

forming a first interconnect layer having a plurality of regions of interconnection metal on the insulating layer opposite the plurality of semiconductor devices;

depositing a first layer of oxide on the first interconnect layer so as to cover at least a portion of the plurality of regions of interconnection metal;

depositing a high dielectric layer on the first layer of oxide opposite the first interconnect layer;

depositing a second layer of oxide on the high dielectric layer opposite the first layer of oxide;

forming a second interconnect layer on the second layer of oxide opposite the high dielectric layer and having a plurality of regions of interconnection metal, wherein a thickness of the first layer of oxide and a thickness of the second layer of oxide are an order of magnitude smaller than a thickness of the high dielectric layer; and

wherein the first layer of oxide, the high dielectric layer and the second layer of oxide are disposed between corresponding ones of the plurality of regions of interconnection metal of the first interconnect layer and the plurality of regions of interconnection metal of the second interconnect layer so as to provide an inter-metal dielectric structure.

6. The method of claim 5, wherein the first oxide layer and the second oxide layer comprise silicon dioxide layers and wherein the high dielectric layer comprises a silicon nitride layer.

7. The method of claim 6, wherein the first oxide layer has a thickness of from about 10 to about 30 nm, the high dielectric layer has a thickness of from about 200 to about 300 nm and the second oxide layer has a thickness of from about 10 to about 30 nm.

8. The method of claim 5, wherein the interconnect metal of the first and second interconnect layers comprises at least one of titanium, platinum, chromium and gold.

9. A method of fabricating a metal-insulator semiconductor capacitor, comprising:

depositing a layer of silicon oxynitride having a formula Si₃N_4-XO_X, where 0<

X≦

1, directly on a silicon carbide layer so as to provide a layer of dielectric material having a first thickness; and

forming a first metal layer on the layer of silicon oxynitride.

10. The method of claim 9, wherein the first thickness is from about 20 nm to about 400 nm.

11. The method of claim 9, wherein depositing a silicon oxynitride layer having a formula Si₃N_4-XO_X, where 0<

X≦

1 comprises;

providing a silicon precursor;

providing a nitrogen precursor;

providing an oxygen precursor; and

depositing the layer of silicon oxynitride utilizing the silicon precursor, the nitrogen precursor and the oxygen precursor utilizing a plasma enhanced chemical vapor deposition (PECVD) process.

12. The method of claim 11, wherein the silicon precursor comprises SiH₄, the oxygen precursor comprises N₂O and the nitrogen precursor comprises N₂.

13. A method of fabricating a metal-insulator-metal capacitor, comprising:

depositing a layer of silicon oxynitride having a formula Si₃N_4-XO_X, where 0<

X≦

1, on a silicon carbide layer so as to provide a layer of dielectric material having a first thickness;

forming a first metal layer on the layer of silicon oxynitride; and

forming a second metal layer disposed between the layer of silicon oxynitride and the silicon carbide layer.

14. The method of claim 13, wherein the first and second metal layers comprise at least one of titanium, platinum, chromium and gold.

15. A method of fabricating a capacitor, comprising:

depositing a layer of silicon oxynitride having a formula Si₃N_4-XO_X, where 0<

X≦

1, on a silicon carbide layer so as to provide a layer of dielectric material having a first thickness;

forming a first metal layer on the layer of silicon oxynitride, wherein depositing a silicon oxynitride layer having a formula Si₃N_4-XO_X, where 0<

X≦

1 comprises;

providing a silicon precursor;

providing a nitrogen precursor;

providing an oxygen precursor; and

depositing the layer of silicon oxynitride utilizing the silicon precursor, the nitrogen precursor and the oxygen precursor utilizing a plasma enhanced chemical vapor deposition (PECVD) process;

wherein the silicon precursor comprises SiH₄, the oxygen precursor comprises N₂O and the nitrogen precursor comprises N₂; and

wherein the SiH₄ is provided at a flow rate of from about 240 to about 360 standard cubic centimeters per minute (SCCM), the N₂O is provided at a flow rate of from about 8 to about 12 SCCM and the N₂ is provided at a flow rate of from about 120 to about 180 SCCM for a PECVD apparatus having a volume of about 14785 cubic centimeters.

16. The method of claim 15, further comprising providing an inert gas.

17. The method of claim 16, wherein the inert gas comprises He provided at a flow rate of from about 160 to about 240 SCCM.

18. The method of claim 15, wherein the PECVD process is carried out at a power of from about 16 to about 24 watts, a pressure of from about 720 to 1080 mT and a temperature of from about 200 to 300°

C.

19. A method of forming a capacitor comprising:

forming a silicon carbide layer;

forming a first oxide layer having a first thickness directly on the silicon carbide layer;

forming a layer of dielectric material on the first oxide layer and having a second thickness, the layer of dielectric material having a dielectric constant higher than the dielectric constant of the first oxide layer;

forming a second oxide layer on the layer of dielectric material opposite the first oxide layer and having a third thickness; and

wherein the first thickness is between about 0.5 and about 33 percent and the third thickness is between about 0.5 and about 33 percent of a sum of the first, second and third thicknesses.