Semiconductor integrated circuit device with reduced leakage current

• US 6,998,674 B2
• Filed: 04/13/2005
• Issued: 02/14/2006
• Est. Priority Date: 06/05/2001
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Kitai, Naoki, Nishida, Akio, Osada, Kenichi, Nakamichi, Masaru, Ishibashi, Koichiro, Saitoh, Yoshikazu
• Primary Examiner(s): LEE, HSIEN MING
• Application Number:
  US11/104,488
• Publication Number:
  US 20050174141A1
• Time in Patent Office: 307 Days
• Field of Search: 257314-316, 257/320, 257/321, 438/241, 438/258, 438/266
• US Class Current: 257/316
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/18 Peripheral circuit regions
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

Claims

1. A semiconductor integrated circuit device comprising:

a plurality of static type memory cells respectively having a pair of load P-channel transistor and a driver N-channel transistor, an insulating layer for use in a gate of either of the load P-channel transistor or the driver N-channel transistor has a thickness of 4 nm or less;

a power line being connected to source electrodes of each of the load P-channel transistors, through which power is supplied to each of the load P-channel transistors; and

a source line being connected to source electrodes of each of the driver N-channel transistors;

wherein a voltage difference between a voltage on the power line and another voltage on the source line is controlled to be set at a first value in an operating mode with a first current flowing from the load P-channel transistor to ground through the driver N-channel transistor, and wherein the voltage difference is further controlled to be set at a second value lower than the first value in a standby mode with another current at least one digit less than the first current.

2. The semiconductor integrated circuit device according to claim 1, wherein the plurality of memory cells are selected to perform read or write data in the operating mode.

3. The semiconductor integrated circuit device according to claim 1 wherein the operating mode and the standby mode are switched on a selecting signal.

4. A semiconductor integrated circuit device comprising:

a plurality of static type memory cells respectively having a pair of load P-channel transistor and a driver N-channel transistor, an insulating layer for use in a gate of either of the load P-channel transistor or the driver N-channel transistor has a thickness of 4 nm or less;

a power line being connected to source electrodes of each of the load P-channel transistors, through which power is supplied to each of the load P-channel transistors; and

a source line being connected to source electrodes of each of the driver N-channel transistors;

wherein a voltage of the power line is controlled to be set at a first potential value in both an operating mode with a first current flowing from the load P-channel transistor to ground through the driver N-channel transistor and a standby mode with another current at least one digit less than the first current;

wherein a voltage of the source line is controlled to be set at a second potential value higher than the first potential value in the operating mode, and set at a third potential value higher than the second potential value in the standby mode; and

wherein a substrate voltage of the drive N-channel transistor is controlled to be set at the second value in both the operating mode and the standby mode.

5. The semiconductor integrated circuit device according to claim 4, wherein the plurality of memory cells are selected to perform read or write data in the operating mode.

6. The semiconductor integrated circuit device according to claim 4, wherein the operating mode and the standby mode are switched on a selecting signal.