Lookup table circuit optionally configurable as two or more smaller lookup tables with independent inputs
First Claim
1. A lookup table (LUT) circuit, comprising:
- a plurality of memory cells;
a plurality of LUT input terminals;
first and second LUT output terminals;
a first multiplexer stage having input terminals coupled to the memory cells, select terminals coupled to at least a first one of the input terminals, and output terminals, a first output terminal of the first multiplexer stage being coupled to the first LUT output terminal;
a second multiplexer stage having input terminals coupled to the output terminals of the first multiplexer stage, select terminals coupled to at least a second one of the input terminals, and an output terminal coupled to the second LUT output terminal; and
a tristate buffer circuit coupled between the first output terminal of the first multiplexer stage and a first input terminal of the second multiplexer stage.
1 Assignment
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Accused Products
Abstract
Lookup table (LUT) circuits can optionally be configured as two or more smaller LUTs having independent input signals. A LUT circuit includes a tristate buffer circuit coupled between first and second multiplexer stages. The data input of the tristate buffer circuit is provided as a first output signal from the LUT circuit. The output of the second multiplexer stage provides the second LUT output signal. The tristate buffer circuit can include a tristate buffer with a pullup and a pulldown on the output terminal. To configure the circuit as a single LUT, the buffer is enabled (tristate disabled), and both the pullup and pulldown are turned off. To configure the circuit as two separate LUTs, the buffer is tristated and either the pullup or the pulldown is enabled. Additional multiplexer stages and tristate buffer circuits can be included to enable the division of the circuit into larger numbers of LUTs.
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Citations
27 Claims
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1. A lookup table (LUT) circuit, comprising:
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a plurality of memory cells; a plurality of LUT input terminals; first and second LUT output terminals; a first multiplexer stage having input terminals coupled to the memory cells, select terminals coupled to at least a first one of the input terminals, and output terminals, a first output terminal of the first multiplexer stage being coupled to the first LUT output terminal; a second multiplexer stage having input terminals coupled to the output terminals of the first multiplexer stage, select terminals coupled to at least a second one of the input terminals, and an output terminal coupled to the second LUT output terminal; and a tristate buffer circuit coupled between the first output terminal of the first multiplexer stage and a first input terminal of the second multiplexer stage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A lookup table (LUT) circuit, comprising:
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a plurality of memory cells; a plurality of LUT input terminals; first, second, and third LUT output terminals; a first multiplexer stage having input terminals coupled to the memory cells, select terminals coupled to at least a first one of the input terminals, and output terminals, a first output terminal of the first multiplexer stage being coupled to the first LUT output terminal; a second multiplexer stage having input terminals coupled to the output terminals of the first multiplexer stage, select terminals coupled to at least a second one of the input terminals, and output terminals, a first output terminal of the second multiplexer stage being coupled to the second LUT output terminal; a third multiplexer stage having input terminals coupled to the output terminals of the second multiplexer stage, select terminals coupled to at least a third one of the input terminals, and an output terminal coupled to the third LUT output terminal; a first tristate buffer circuit coupled between a first output terminal of the first multiplexer stage and a first input terminal of the second multiplexer stage; and a second tristate buffer circuit coupled between a first output terminal of the second multiplexer stage and a first input terminal of the third multiplexer stage. - View Dependent Claims (13, 14)
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15. A programmable logic device (PLD), comprising:
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an interconnect structure; and a plurality of lookup table (LUT) circuits programmably coupled to the interconnect structure, each LUT circuit comprising; a plurality of memory cells; a plurality of LUT input terminals programmably coupled to the interconnect structure; first and second LUT output terminals programmably coupled to the interconnect structure; a first multiplexer stage having input terminals coupled to the memory cells, select terminals coupled to at least a first one of the input terminals, and output terminals, a first output terminal of the first multiplexer stage being coupled to the first LUT output terminal; a second multiplexer stage having input terminals coupled to the output terminals of the first multiplexer stage, select terminals coupled to at least a second one of the input terminals, and an output terminal coupled to the second LUT output terminal; and a tristate buffer circuit coupled between a first output terminal of the first multiplexer stage and a first input terminal of the second multiplexer stage. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A programmable logic device (PLD), comprising:
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an interconnect structure; and a plurality of lookup table (LUT) circuits programmably coupled to the interconnect structure, each LUT circuit comprising; a plurality of memory cells; a plurality of LUT input terminals; first, second, and third LUT output terminals; a first multiplexer stage having input terminals coupled to the memory cells, select terminals coupled to at least a first one of the input terminals, and output terminals, a first output terminal of the first multiplexer stage being coupled to the first LUT output terminal; a second multiplexer stage having input terminals coupled to the output terminals of the first multiplexer stage, select terminals coupled to at least a second one of the input terminals, and output terminals, a first output terminal of the second multiplexer stage being coupled to the second LUT output terminal; a third multiplexer stage having input terminals coupled to the output terminals of the second multiplexer stage, select terminals coupled to at least a third one of the input terminals, and an output terminal coupled to the third LUT output terminal; a first tristate buffer circuit coupled between a first output terminal of the first multiplexer stage and a first input terminal of the second multiplexer stage; and a second tristate buffer circuit coupled between a first output terminal of the second multiplexer stage and a first input terminal of the third multiplexer stage. - View Dependent Claims (26, 27)
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Specification