Lookup table circuit optionally configurable as two or more smaller lookup tables with independent inputs

• US 6,998,872 B1
• Filed: 06/02/2004
• Issued: 02/14/2006
• Est. Priority Date: 06/02/2004
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Chirania, Manoj, Kondapalli, Venu M.
• Primary Examiner(s): Tran, Anh Q.
• Application Number:
  US10/859,836
• Time in Patent Office: 622 Days
• Field of Search: 326 37- 41, 326/47, 326/113
• US Class Current: 326/40
• CPC Class Codes: H03K 19/1736 in which the wiring can be modified
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables

Abstract

Lookup table (LUT) circuits can optionally be configured as two or more smaller LUTs having independent input signals. A LUT circuit includes a tristate buffer circuit coupled between first and second multiplexer stages. The data input of the tristate buffer circuit is provided as a first output signal from the LUT circuit. The output of the second multiplexer stage provides the second LUT output signal. The tristate buffer circuit can include a tristate buffer with a pullup and a pulldown on the output terminal. To configure the circuit as a single LUT, the buffer is enabled (tristate disabled), and both the pullup and pulldown are turned off. To configure the circuit as two separate LUTs, the buffer is tristated and either the pullup or the pulldown is enabled. Additional multiplexer stages and tristate buffer circuits can be included to enable the division of the circuit into larger numbers of LUTs.

Claims

1. A lookup table (LUT) circuit, comprising:

a plurality of memory cells;

a plurality of LUT input terminals;

first and second LUT output terminals;

a first multiplexer stage having input terminals coupled to the memory cells, select terminals coupled to at least a first one of the input terminals, and output terminals, a first output terminal of the first multiplexer stage being coupled to the first LUT output terminal;

a second multiplexer stage having input terminals coupled to the output terminals of the first multiplexer stage, select terminals coupled to at least a second one of the input terminals, and an output terminal coupled to the second LUT output terminal; and

a tristate buffer circuit coupled between the first output terminal of the first multiplexer stage and a first input terminal of the second multiplexer stage.

2. The LUT circuit of claim 1, wherein the tristate buffer circuit comprises:

a data input terminal coupled to the first output terminal of the first multiplexer stage;

a data output terminal coupled to the first input terminal of the second multiplexer stage;

a tristate buffer having an input terminal coupled to the data input terminal, an output terminal coupled to the data output terminal, and an enable terminal;

a pullup circuit coupled to the data output terminal and having an enable terminal;

a pulldown circuit coupled to the data output terminal and having an enable terminal; and

a control circuit coupled to the enable terminals of the pullup circuit, the pulldown circuit, and the tristate buffer.

3. The LUT circuit of claim 2, wherein the control circuit comprises:

a first memory cell coupled to the enable terminal of the pullup circuit;

a second memory cell coupled to the enable terminal of the pulldown circuit; and

a tristate enable control circuit coupled to the enable terminal of the tristate buffer.

4. The LUT circuit of claim 3, wherein the LUT circuit forms a portion of a programmable logic device (PLD).

5. The LUT circuit of claim 4, wherein the PLD is an FPGA, and the first and second memory cells comprise configuration memory cells of the FPGA.

6. The LUT circuit of claim 3, wherein the tristate enable control circuit comprises a third memory cell.

7. The LUT circuit of claim 3, wherein the tristate enable control circuit comprises a logic gate having input terminals coupled to the first and second memory cells and an output terminal coupled to the enable terminal of the tristate buffer.

8. The LUT circuit of claim 7, wherein the logic gate is a logical NAND gate.

9. The LUT circuit of claim 1, further comprising a plurality of inverting logic gates, and wherein the first and second multiplexer stages each comprise a plurality of CMOS pass gates coupled between the input terminals and the output terminals of a corresponding multiplexer stage, the CMOS pass gates having first gate terminals coupled to the LUT input terminals and second gate terminals coupled to the LUT input terminals via the inverting logic gates.

10. The LUT circuit of claim 1, wherein the first and second multiplexer stages each comprise a plurality of N-channel transistors coupled between the input terminals and the output terminals of a corresponding multiplexer stage, the N-channel transistors having gate terminals coupled to the LUT input terminals.

11. The LUT circuit of claim 10, further comprising a plurality of pullup circuits each coupled to a corresponding output terminal of the first multiplexer stage, each pullup circuit having an enable terminal coupled to an input terminal of the second multiplexer stage.

12. A lookup table (LUT) circuit, comprising:

a plurality of memory cells;

a plurality of LUT input terminals;

first, second, and third LUT output terminals;

a first multiplexer stage having input terminals coupled to the memory cells, select terminals coupled to at least a first one of the input terminals, and output terminals, a first output terminal of the first multiplexer stage being coupled to the first LUT output terminal;

a second multiplexer stage having input terminals coupled to the output terminals of the first multiplexer stage, select terminals coupled to at least a second one of the input terminals, and output terminals, a first output terminal of the second multiplexer stage being coupled to the second LUT output terminal;

a third multiplexer stage having input terminals coupled to the output terminals of the second multiplexer stage, select terminals coupled to at least a third one of the input terminals, and an output terminal coupled to the third LUT output terminal;

a first tristate buffer circuit coupled between a first output terminal of the first multiplexer stage and a first input terminal of the second multiplexer stage; and

a second tristate buffer circuit coupled between a first output terminal of the second multiplexer stage and a first input terminal of the third multiplexer stage.

13. The LUT circuit of claim 12, wherein each of the first and second tristate buffer circuits comprises:

a data input terminal coupled to the first output terminal of a corresponding preceding multiplexer stage;

a data output terminal coupled to the first input terminal of a corresponding following multiplexer stage;

a tristate buffer having an input terminal coupled to the data input terminal, an output terminal coupled to the data output terminal, and an enable terminal;

a pullup circuit coupled to the data output terminal and having an enable terminal;

a pulldown circuit coupled to the data output terminal and having an enable terminal; and

a control circuit coupled to the enable terminals of the pullup circuit, the pulldown circuit, and the tristate buffer.

14. The LUT circuit of claim 13, wherein the LUT circuit forms a portion of a programmable logic device (PLD), and the control circuit comprises a plurality of configuration memory cells for the PLD.

15. A programmable logic device (PLD), comprising:

an interconnect structure; and

a plurality of lookup table (LUT) circuits programmably coupled to the interconnect structure, each LUT circuit comprising;

a plurality of memory cells;

a plurality of LUT input terminals programmably coupled to the interconnect structure;

first and second LUT output terminals programmably coupled to the interconnect structure;

a first multiplexer stage having input terminals coupled to the memory cells, select terminals coupled to at least a first one of the input terminals, and output terminals, a first output terminal of the first multiplexer stage being coupled to the first LUT output terminal;

a second multiplexer stage having input terminals coupled to the output terminals of the first multiplexer stage, select terminals coupled to at least a second one of the input terminals, and an output terminal coupled to the second LUT output terminal; and

a tristate buffer circuit coupled between a first output terminal of the first multiplexer stage and a first input terminal of the second multiplexer stage.

16. The PLD of claim 15, wherein the tristate buffer circuit comprises:

a data input terminal coupled to the first output terminal of the first multiplexer stage;

a data output terminal coupled to the first input terminal of the second multiplexer stage;

a tristate buffer having an input terminal coupled to the data input terminal, an output terminal coupled to the data output terminal, and an enable terminal;

a pullup circuit coupled to the data output terminal and having an enable terminal;

a pulldown circuit coupled to the data output terminal and having an enable terminal; and

a control circuit coupled to the enable terminals of the pullup circuit, the pulldown circuit, and the tristate buffer.

17. The PLD of claim 16, wherein the control circuit comprises:

a first memory cell coupled to the enable terminal of the pullup circuit;

a second memory cell coupled to the enable terminal of the pulldown circuit; and

a tristate enable control circuit coupled to the enable terminal of the tristate buffer.

18. The PLD of claim 17, wherein the PLD is an FPGA, and the first and second memory cells comprise configuration memory cells of the FPGA.

19. The PLD of claim 17, wherein the tristate enable control circuit comprises a third memory cell.

20. The PLD of claim 17, wherein the tristate enable control circuit comprises a logic gate having input terminals coupled to the first and second memory cells and an output terminal coupled to the enable terminal of the tristate buffer.

21. The PLD of claim 20, wherein the logic gate is a logical NAND gate.

22. The PLD of claim 15, wherein each LUT circuit further comprises a plurality of inverting logic gates, and wherein the first and second multiplexer stages each comprise a plurality of CMOS pass gates coupled between the input terminals and the output terminals of a corresponding multiplexer stage, the CMOS pass gates having first gate terminals coupled to the LUT input terminals and second gate terminals coupled to the LUT input terminals via the inverting logic gates.

23. The PLD of claim 15, wherein the first and second multiplexer stages each comprise a plurality of N-channel transistors coupled between the input terminals and the output terminals of a corresponding multiplexer stage, the N-channel transistors having gate terminals coupled to the LUT input terminals.

24. The PLD of claim 23, further comprising a plurality of pullup circuits each coupled to a corresponding output terminal of the first multiplexer stage, each pullup circuit having an enable terminal coupled to an input terminal of the second multiplexer stage.

25. A programmable logic device (PLD), comprising:

an interconnect structure; and

a plurality of lookup table (LUT) circuits programmably coupled to the interconnect structure, each LUT circuit comprising;

a plurality of memory cells;

a plurality of LUT input terminals;

first, second, and third LUT output terminals;

a first multiplexer stage having input terminals coupled to the memory cells, select terminals coupled to at least a first one of the input terminals, and output terminals, a first output terminal of the first multiplexer stage being coupled to the first LUT output terminal;

a second multiplexer stage having input terminals coupled to the output terminals of the first multiplexer stage, select terminals coupled to at least a second one of the input terminals, and output terminals, a first output terminal of the second multiplexer stage being coupled to the second LUT output terminal;

a third multiplexer stage having input terminals coupled to the output terminals of the second multiplexer stage, select terminals coupled to at least a third one of the input terminals, and an output terminal coupled to the third LUT output terminal;

a first tristate buffer circuit coupled between a first output terminal of the first multiplexer stage and a first input terminal of the second multiplexer stage; and

a second tristate buffer circuit coupled between a first output terminal of the second multiplexer stage and a first input terminal of the third multiplexer stage.

26. The PLD of claim 25, wherein each of the first and second tristate buffer circuits comprises:

a data input terminal coupled to the first output terminal of a corresponding preceding multiplexer stage;

a data output terminal coupled to the first input terminal of a corresponding following multiplexer stage;

a tristate buffer having an input terminal coupled to the data input terminal, an output terminal coupled to the data output terminal, and an enable terminal;

a pullup circuit coupled to the data output terminal and having an enable terminal;

a pulldown circuit coupled to the data output terminal and having an enable terminal; and

a control circuit coupled to the enable terminals of the pullup circuit, the pulldown circuit, and the tristate buffer.

27. The PLD of claim 26, wherein each of the control circuits comprises a plurality of configuration memory cells for the PLD.