Non-volatile semiconductor memory device and electric device with the same

• US 6,999,344 B2
• Filed: 03/11/2005
• Issued: 02/14/2006
• Est. Priority Date: 04/22/2003
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nakamura, Hiroshi, Hosono, Koji, Imamiya, Kenichi
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US11/077,640
• Publication Number:
  US 20050157564A1
• Time in Patent Office: 340 Days
• Field of Search: 365/185.17, 365/185.21, 365/185.22, 365/189.05, 365/185.33, 365/51, 365/52, 365/63
• US Class Current: 365/185.17
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2211/5643 Multilevel memory comprising cache storage devices

Abstract

A non-volatile semiconductor memory device includes: a memory cell array in which electrically rewritable floating gate type memory cells are arranged; and a plurality of sense amplifier circuits configured to read data from the memory cell array, wherein each the sense amplifier circuit is configured to sense cell data of a first memory cell selected from the memory cell array under a read condition determined in correspondence with cell data of a second memory cell adjacent to the first memory cell and written after the first memory cell.

Claims

1. A non-volatile semiconductor memory device comprising:

a memory cell array in which electrically rewritable memory cells are arranged; and

a plurality of sense amplifier circuits configured to read data from said memory cell array,

wherein each said sense amplifier circuit comprises a first circuit temporarily holding data of a first memory cell selected by address data input from outside, and a second circuit temporarily holding data of a second memory cell which is adjacent to said first memory cell, in which a writing operation is conducted after a writing operation to said first memory cell, and in which a reading operation is conducted before a reading operation to said first memory cell.

2. The non-volatile semiconductor memory device according to claim 1, wherein said data held in said second circuit is data showing whether threshold value of said second memory cell has been changed after a writing operation to said first memory cell.

3. The non-volatile semiconductor memory device according to claim 2, wherein said data in said first memory cell is read under plural read conditions determined by data held in said second circuit.

4. The non-volatile semiconductor memory device according to claim 3, wherein said plural read conditions are different in voltage to a word line of said first memory cell.

5. The non-volatile semiconductor memory device according to claim 3, wherein said plural read conditions are different in bit-line discharge time during a read operation in said first memory cell.

6. The non-volatile semiconductor memory device according to claim 1, wherein data held in said second circuit is read from said second memory cell after address data of said first memory cells is input from outside to read data in said first memory cells, and before reading data in said first memory cell for storage in said first circuit.

7. The non-volatile semiconductor memory device according to claim 3, wherein when address data of said first memory cells is input from outside to read data in said first memory cell, and there is no memory cell which is adjacent to said first memory cell and in which a writing operation is conducted after a writing operation to said first memory cell, data in said first memory cell is read under a certain read condition.

8. The non-volatile semiconductor memory device according to claim 1, wherein each of said memory cells is capable of discriminating and storing data of 2 bits or more.

9. The non-volatile semiconductor memory device according to claim 1, wherein

said memory cell array comprises a plurality of NAND cell units arranged therein, each NAND cell unit having a serial circuit of a plurality of memory cells, a first select gate transistor disposed between one end of said serial circuit and a bit line, and a second select gate transistor disposed between the other end of said serial circuit and a common source line, each said memory cell having a floating gate and a control gate stacked thereabove.

10. The non-volatile semiconductor memory device according to claim 9, wherein

the control gates of said memory cells in each said NAND cell unit are connected to different word lines, respectively, and wherein

the gates of said first and second select gate transistors in each said NAND cell unit are connected to select gate lines, respectively.

11. The non-volatile semiconductor memory device according to claim 10, wherein

a plurality of memory cells arranged along a word line and connected to different bit lines, respectively, constitute a page which serves as a unit for parallel data read and parallel dada write, and wherein

said plurality of sense amplifier circuits constitute a page buffer for sensing data of one page.

12. A memory system comprising:

a non-volatile semiconductor memory device,

a cache memory for temporarily storing data input to and output from said non-volatile semiconductor memory device; and

a controller for controlling dada transfer between said cache memory and said non-volatile semiconductor memory device in such a manner that a data write operation of said non-volatile semiconductor memory device is performed for a write region directed from external in order from the uppermost address of said write region,

wherein said nonvolatile memory device comprises;

a memory cell array in which electrically rewritable floating gate type memory cells are arranged; and

a plurality of sense amplifier circuits configured to read data from said memory cell array, wherein

each of said sense amplifier circuits is configured to sense cell data of a first memory cell selected from said memory cell array under a read condition determined in correspondence with cell data of a second memory cell adjacent to said first memory cell and written after said first memory cell,

and wherein each said sense amplifier circuit comprises a first circuit for holding a read data of said first memory cell and a second circuit for holding a data read out from said second memory cell prior to data read of said first memory cell as a reference data.

13. The memory system according to claim 12, wherein

said non-volatile semiconductor memory device comprises a plurality of cell blocks each serving as a unit for a data erase in a lump, and wherein

said cache memory has a data storing area with a capacity larger than that of each said cell block, and wherein

said controller controls to store data, which is to be written into a cell block of said non-volatile semiconductor memory device, in said cache memory, and then transfer the stored data to said non-volatile semiconductor memory device, thereby starting a data write operation.

14. An electric card equipped with a non-volatile semiconductor memory device, wherein said nonvolatile memory device comprising:

a memory cell array in which electrically rewritable floating gate type memory cells are arranged; and

a plurality of sense amplifier circuits configured to read data from said memory cell array, wherein

each of said sense amplifier circuits is configured to sense cell data of a first memory cell selected from said memory cell array under a read condition determined in correspondence with cell data of a second memory cell adjacent to said first memory cell and written after said first memory cell,

and wherein each said sense amplifier circuit comprises a first circuit for holding a read data of said first memory cell and a second circuit for holding a data read out from said second memory cell prior to data read of said first memory cell as a reference data.

15. An electric card equipped with a memory system, comprising:

a non-volatile semiconductor memory device,

a cache memory for temporarily storing data input to and output from said non-volatile semiconductor memory device; and

a controller for controlling dada transfer between said cache memory and said non-volatile semiconductor memory device in such a manner that a data write operation of said non-volatile semiconductor memory device is performed for a write region directed from external in order from the uppermost address of said write region,

wherein said nonvolatile memory device comprises;

a memory cell array in which electrically rewritable floating gate type memory cells are arranged; and

a plurality of sense amplifier circuits configured to read data from said memory cell array, wherein

each of said sense amplifier circuits is configured to sense cell data of a first memory cell selected from said memory cell array under a read condition determined in correspondence with cell data of a second memory cell adjacent to said first memory cell and written after said first memory cell,

wherein each said sense amplifier circuit comprises a first circuit for holding a read data of said first memory cell and a second circuit for holding a data read out from said second memory cell prior to data read of said first memory cell as a reference data,

wherein said non-volatile semiconductor memory device comprises a plurality of cell blocks each serving as a unit for a data erase in a lump, and wherein

said cache memory has a data storing area with a capacity larger than that of each said cell block, and wherein

said controller controls to store data, which is to be written into a cell block of said non-volatile semiconductor memory device, in said cache memory, and then transfer the stored data to said non-volatile semiconductor memory device, thereby starting a data write operation.

16. An electric device comprising:

a card interface;

a card slot connected to said card interface; and

an electric card electrically connectable to said card slot, wherein said electronic card is equipped with a non-volatile semiconductor memory device, wherein said nonvolatile memory device comprises;

a memory cell array in which electrically rewritable floating gate type memory cells are arranged; and

a plurality of sense amplifier circuits configured to read data from said memory cell array, wherein

each of said sense amplifier circuits is configured to sense cell data of a first memory cell selected from said memory cell array under a read condition determined in correspondence with cell data of a second memory cell adjacent to said first memory cell and written after said first memory cell,

and wherein each said sense amplifier circuit comprises a first circuit for holding a read data of said first memory cell and a second circuit for holding a data read out from said second memory cell prior to data read of said first memory cell as a reference data.

18. The electric device according to claim 16, wherein said electric device is a digital still camera.

17. An electric device comprising:

a card interface;

a card slot connected to said card interface; and

an electric card electrically connectable to said card slot, wherein said electric card is equipped with a memory system, comprising;

a non-volatile semiconductor memory device,

a cache memory for temporarily storing data input to and output from said non-volatile semiconductor memory device; and

a controller for controlling dada transfer between said cache memory and said non-volatile semiconductor memory device in such a manner that a data write operation of said non-volatile semiconductor memory device is performed for a write region directed from external in order from the uppermost address of said write region,

wherein said nonvolatile memory device comprising;

a memory cell array in which electrically rewritable floating gate type memory cells are arranged; and

a plurality of sense amplifier circuits configured to read data from said memory cell array, wherein

each of said sense amplifier circuits is configured to sense cell data of a first memory cell selected from said memory cell array under a read condition determined in correspondence with cell data of a second memory cell adjacent to said first memory cell and written after said first memory cell,

and wherein each said sense amplifier circuit comprises a first circuit for holding a read data of said first memory cell and a second circuit for holding a data read out from said second memory cell prior to data read of said first memory cell as a reference data.

19. The electric device according to claim 17, wherein said electric device is a digital still camera.