Method for screening failure of memory cell transistor

• US 6,999,359 B2
• Filed: 05/21/2004
• Issued: 02/14/2006
• Est. Priority Date: 03/11/2004
• Status: Active Grant

• Current Assignee: Intellectual Discovery Co., Ltd.
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kim, Young Soo, Lee, Jung Hoon
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US10/850,622
• Publication Number:
  US 20050201166A1
• Time in Patent Office: 634 Days
• Field of Search: 365/200, 365/201, 365/205
• US Class Current: 365/200
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

The present invention discloses a method for screening a sensing margin generated by a gate residue in a memory cell transistor. The method for screening failure of the memory cell transistor is summarized as follows. A test mode signal for sensing margin control is supplied. A write operation is performed to store data in the cell transistor. A word line is enabled by an active command. Isolated transistors disposed between a bit line coupled to the cell transistor and a bit line coupled to a sense amplifier are disabled to intercept a sensing operation. A voltage of the bit line coupled to the cell transistor is measured for a predetermined time. Here, voltage variations on the bit line are measured to screen failure of the cell transistor.

Claims

1. A method for screening failure of a memory cell transistor for a memory device, comprising the steps of:

(s1) enabling a word line coupled to the memory cell transistor;

(s2) disabling isolated transistors disposed between a first bit line on which the memory cell transistor is positioned and a second bit line on which the sense amplifier is positioned; and

(s3) screening voltage variations on the first bit line for a predetermined time.

2. The method of claim 1, wherein, when a first control signal for enabling the word line and a test mode signal for screening failure of the memory cell transistor are enabled at the same time, the isolated transistors are disabled.

3. The method of claim 1, further comprising the step of:

(s4) enabling the sense amplifier to perform a turn-on operation by turning on the isolated transistors.

4. A method for screening failure of a memory cell transistor for a memory device, comprising the steps of:

(s1) supplying a test mode signal;

(s2) enabling a word line coupled to the memory cell transistor;

(s3) disabling isolated transistors disposed between a first bit line on which the memory cell transistor is positioned and a second bit line on which the sense amplifier is positioned; and

(s4) screening voltage variations on the first bit line for a predetermined time.

5. The method of claim 4, further comprising the step of:

(s5) enabling the sense amplifier to perform a turn-on operation by turning on the isolated transistors.

6. A method for screening failure of a memory cell transistor, comprising the steps of:

(s1) supplying a test mode signal for sensing margin control;

(s2) performing a write operation to store data in the cell transistor;

(s3) enabling a word line by an active command;

(s4) disabling isolated transistors disposed between a bit line coupled to the cell transistor and a bit line coupled to the sense amplifier; and

(s5) measuring a voltage of the bit line coupled to the cell transistor for a predetermined time.

7. The method of claim 6, further comprising the step of:

(s6) enabling the sense amplifier to perform a turn-on operation by turning on the isolated transistors.