Shift redundancy circuit, method for controlling shift redundancy circuit, and semiconductor memory device
First Claim
1. A method for controlling a shift redundancy circuit that selectively connects a plurality of selection lines and at least one redundancy selection line, each of which commonly shares a plurality of memory blocks, to a plurality of decode selection lines, and remedies a deficiency relating to each of the plurality of selection lines for each memory block, the method comprising the steps of:
- decoding a deficiency address indicating a deficient location to generate a decode signal;
generating a shift signal for determining the plurality of decode selection lines to be selectively connected to the plurality of selection lines and the at least one redundancy selection line based on the decode signal for each memory block having a deficiency to be remedied;
selecting a shift signal corresponding to a selected memory block having a deficiency to be remedied based on a memory block selection signal; and
selectively connecting the plurality of decode selection lines to the plurality of selection lines and the at least one redundancy selection line based on the selected shift signal.
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0 Petitions
Accused Products
Abstract
A shift redundancy circuit for enabling switching operation of memory blocks to be executed at a high speed and for reducing current consumption relating to the switching operation. A shift control circuit includes a first shift control circuit for generating a first shift signal corresponding to a first deficiency address of a memory block and a second shift control circuit for generating a second shift signal corresponding to a second deficiency address of a memory block. When the memory blocks are switched, a shift signal controlling the switching of selection line switches are selected from the first shift signal whose state is determined in advance, the second shift signal whose state is determined in advance, and a low potential power supply.
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Citations
12 Claims
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1. A method for controlling a shift redundancy circuit that selectively connects a plurality of selection lines and at least one redundancy selection line, each of which commonly shares a plurality of memory blocks, to a plurality of decode selection lines, and remedies a deficiency relating to each of the plurality of selection lines for each memory block, the method comprising the steps of:
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decoding a deficiency address indicating a deficient location to generate a decode signal; generating a shift signal for determining the plurality of decode selection lines to be selectively connected to the plurality of selection lines and the at least one redundancy selection line based on the decode signal for each memory block having a deficiency to be remedied; selecting a shift signal corresponding to a selected memory block having a deficiency to be remedied based on a memory block selection signal; and selectively connecting the plurality of decode selection lines to the plurality of selection lines and the at least one redundancy selection line based on the selected shift signal. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A shift redundancy circuit for selectively connecting a plurality of selection lines and at least one redundancy selection line, each of which commonly shares a plurality of memory blocks, to a plurality of decode selection lines, and remedying a deficiency relating to each of the plurality of selection lines for each memory block, the circuit comprising:
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a shift control circuit for generating a shift signal for determining the plurality of decode selection lines to be selectively connected to the plurality of selection lines and the at least one redundancy selection line based on a deficiency address indicating a deficient location and a redundancy selection signal for selecting the redundancy selection line for each memory block having a deficiency to be remedied; a shift signal selection circuit, connected to the shift control circuit, for selecting a shift signal corresponding to a selected memory block having a deficiency to be remedied based on a memory block selection signal; and a switch circuit, connected to the shift signal selection circuit, for selectively connecting the plurality of decode selection lines to the plurality of selection lines and the at least one redundancy selection line based on the shift signal selected by the shift signal selection circuit. - View Dependent Claims (8, 9, 10, 11)
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12. A semiconductor memory device comprising:
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a plurality of memory blocks; a plurality of selection lines and at least one redundancy selection line, each of which commonly shares the plurality of memory blocks; a plurality of decode selection lines; and a shift redundancy circuit for selectively connecting the plurality of selection lines and the at least one redundancy selection line to the plurality of decode selection lines, and remedying a deficiency relating to each of the plurality of selection lines for each memory block, wherein the shift redundancy circuit includes; a shift control circuit for generating, for each memory block having a deficiency to be remedied, a shift signal for determining the plurality of decode selection lines to be selectively connected to the plurality of selection lines and the at least one redundancy selection line based on a deficiency address indicating a deficient location and a redundancy selection signal for selecting the redundancy selection line; a shift signal selection circuit, connected to the shift control circuit, for selecting a shift signal corresponding to a selected memory block having a deficiency to be remedied based on a memory block selection signal; and a switch circuit, connected to the shift signal selection circuit, for selectively connecting the plurality of decode selection lines to the plurality of selection lines and the at least one redundancy selection line based on the shift signal selected by the shift signal selection circuit.
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Specification