Shift redundancy circuit, method for controlling shift redundancy circuit, and semiconductor memory device

• US 6,999,360 B2
• Filed: 01/25/2005
• Issued: 02/14/2006
• Est. Priority Date: 02/18/2003
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Komura, Kazufumi
• Primary Examiner(s): PHUNG, ANH K
• Application Number:
  US11/041,287
• Publication Number:
  US 20050122804A1
• Time in Patent Office: 385 Days
• Field of Search: 365/200, 365/189.12, 365/230.03, 365/230.06
• US Class Current: 365/200
• CPC Class Codes: G11C 29/848 by adjacent switching

Abstract

A shift redundancy circuit for enabling switching operation of memory blocks to be executed at a high speed and for reducing current consumption relating to the switching operation. A shift control circuit includes a first shift control circuit for generating a first shift signal corresponding to a first deficiency address of a memory block and a second shift control circuit for generating a second shift signal corresponding to a second deficiency address of a memory block. When the memory blocks are switched, a shift signal controlling the switching of selection line switches are selected from the first shift signal whose state is determined in advance, the second shift signal whose state is determined in advance, and a low potential power supply.

Claims

1. A method for controlling a shift redundancy circuit that selectively connects a plurality of selection lines and at least one redundancy selection line, each of which commonly shares a plurality of memory blocks, to a plurality of decode selection lines, and remedies a deficiency relating to each of the plurality of selection lines for each memory block, the method comprising the steps of:

decoding a deficiency address indicating a deficient location to generate a decode signal;

generating a shift signal for determining the plurality of decode selection lines to be selectively connected to the plurality of selection lines and the at least one redundancy selection line based on the decode signal for each memory block having a deficiency to be remedied;

selecting a shift signal corresponding to a selected memory block having a deficiency to be remedied based on a memory block selection signal; and

selectively connecting the plurality of decode selection lines to the plurality of selection lines and the at least one redundancy selection line based on the selected shift signal.

2. The method for controlling a shift redundancy circuit according to claim 1, wherein the step for generating a decode signal includes decoding the deficiency address based on a redundancy selection signal to generate a decode signal.

3. The method for controlling a shift redundancy circuit according to claim 1, wherein the step for generating a decode signal includes decoding the deficiency address for each memory block having a deficiency to be remedied to generate a decode signal.

4. The method for controlling a shift redundancy circuit according to claim 1, further comprising:

the step of clamping the shift signal to a predetermined power supply potential so that the plurality of decode selection lines are respectively connected to the plurality of selection lines when no memory block having a deficiency to be remedied is selected based on the memory block selection signal.

5. The method for controlling a shift redundancy circuit according to claim 1, further comprising the step of:

generating memory block selection signals so that the number of the memory block selection signals corresponds to the number of memory blocks having a deficiency to be remedied.

6. The method for controlling a shift redundancy circuit according to claim 1, further comprising the step of:

generating the memory block selection signal based on a decoding result of a block address signal and block selection information corresponding to the block address signal.

7. A shift redundancy circuit for selectively connecting a plurality of selection lines and at least one redundancy selection line, each of which commonly shares a plurality of memory blocks, to a plurality of decode selection lines, and remedying a deficiency relating to each of the plurality of selection lines for each memory block, the circuit comprising:

a shift control circuit for generating a shift signal for determining the plurality of decode selection lines to be selectively connected to the plurality of selection lines and the at least one redundancy selection line based on a deficiency address indicating a deficient location and a redundancy selection signal for selecting the redundancy selection line for each memory block having a deficiency to be remedied;

a shift signal selection circuit, connected to the shift control circuit, for selecting a shift signal corresponding to a selected memory block having a deficiency to be remedied based on a memory block selection signal; and

a switch circuit, connected to the shift signal selection circuit, for selectively connecting the plurality of decode selection lines to the plurality of selection lines and the at least one redundancy selection line based on the shift signal selected by the shift signal selection circuit.

8. The shift redundancy circuit according to claim 7, wherein the shift control circuit includes a plurality of shift control circuits, the number of the shift control circuits corresponding to the number of memory blocks having a deficiency to be remedied.

9. The shift redundancy circuit according to claim 7, further comprising:

a deficiency address hold circuit for holding the deficiency address for each memory block having a deficiency to be remedied; and

a redundancy selection signal generation circuit for holding the redundancy selection signal for each memory block having a deficiency to be remedied.

10. The shift redundancy circuit according to claim 7, wherein:

the switch circuit includes a plurality of selection line switches, corresponding to the plurality of selection lines, and at least one redundancy selection line switch, corresponding to the at least one redundancy selection line; and

the shift control circuit includes a first switch control circuit, for controlling the at least one redundancy selection line switch, and a plurality of second switch control circuits, for respectively controlling the plurality of selection line switches.

11. The shift redundancy circuit according to claim 7, wherein the shift signal selection circuit includes a means for clamping the shift signal to a predetermined power supply potential so that the plurality of decode selection lines are respectively connected to the plurality of selection lines when no memory block having a deficiency to be remedied is selected based on the memory block selection signal.

12. A semiconductor memory device comprising:

a plurality of memory blocks;

a plurality of selection lines and at least one redundancy selection line, each of which commonly shares the plurality of memory blocks;

a plurality of decode selection lines; and

a shift redundancy circuit for selectively connecting the plurality of selection lines and the at least one redundancy selection line to the plurality of decode selection lines, and remedying a deficiency relating to each of the plurality of selection lines for each memory block, wherein the shift redundancy circuit includes;

a shift control circuit for generating, for each memory block having a deficiency to be remedied, a shift signal for determining the plurality of decode selection lines to be selectively connected to the plurality of selection lines and the at least one redundancy selection line based on a deficiency address indicating a deficient location and a redundancy selection signal for selecting the redundancy selection line;

a shift signal selection circuit, connected to the shift control circuit, for selecting a shift signal corresponding to a selected memory block having a deficiency to be remedied based on a memory block selection signal; and

a switch circuit, connected to the shift signal selection circuit, for selectively connecting the plurality of decode selection lines to the plurality of selection lines and the at least one redundancy selection line based on the shift signal selected by the shift signal selection circuit.