Multi-interface symmetric multiprocessor

• US 7,000,055 B1
• Filed: 07/26/2002
• Issued: 02/14/2006
• Est. Priority Date: 11/29/1999
• Status: Expired due to Term

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Robins, Kristen Marie, Kon, Ronnie B.
• Primary Examiner(s): Myers, Paul R.
• Application Number:
  US10/206,906
• Time in Patent Office: 1,299 Days
• Field of Search: 710/305, 710 52- 57, 710/310, 709/213, 709/232, 709/102, 709/200, 370412-413, 370/419
• US Class Current: 710/305
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B

Abstract

A symmetric multiprocessor system includes a first processor and a second processor for executing a multi-threaded process on packets, a first inbound interface and a first outbound interface associated with the first processor, a first task queue accessible for reading by the first processor, a second inbound interface and a second outbound interface associated with the second processor, and a second task queue accessible for reading by at least the first processor. The first inbound interface receives incoming packets and has a first input buffer maintaining a first input queue of the packets for processing by the first processor. The first outbound interface receives packets from the first processor and transmits outgoing packets. The first task queue receives packets output from at least the second processor and maintains another input queue of the packets for processing by the first processor and which are outgoing from the first outbound interface. The second inbound interface receives incoming packets and has a second input buffer maintaining a second input queue of the packets. The second outbound interface receives packets from the second processor and transmits outgoing packets. The second task queue receives packets output from at least the first processor and maintains another input queue of the packets for processing by the second processor and which are outgoing from the second outbound interface. The first processor executes a process thread on packets by requesting the packets from the first input queue and the first task queue in a predetermined manner. The second processor executes a process thread on packets by requesting the packets from the second input queue and the second task queue in a predetermined manner.

Claims

1. A symmetric multiprocessor system comprising:

a first processor;

a first inbound interface associated with said first processor, said first inbound interface receiving tasks for processing by said first processor;

a first outbound interface associated with said first processor, said first outbound interface capable of receiving an output associated with tasks performed by said first processor;

a second processor;

a task queue readable by said second processor and writable by said first processor, said task queue receiving tasks for processing by said second processor; and

a second outbound interface associated with said second processor, said second outbound interface capable of receiving an output associated with tasks performed by said second processor.

2. A symmetric multiprocessor system comprising:

a first processor and a second processor for executing a multi-threaded process on packets;

a first inbound interface device associated with said first processor, said first inbound interface device receiving incoming packets and having a first input buffer accessible by said first processor, said first input buffer maintaining a queue of the packets received on said first inbound interface device;

a first outbound interface device associated with said first processor, said first outbound interface device receiving packets output from said first processor and transmitting said packets therefrom;

a second outbound interface device associated with said second processor, said second outbound interface receiving packets output from said second processor and transmitting said packets therefrom; and

a task queue accessible for reading by said second processor, said task queue receiving packets output from at least said first processor, the packets in said task queue being transmitted from said second outbound interface device.

3. A symmetric multiprocessor system comprising:

a first processor and a second processor for executing a multi-threaded process on packets;

a first inbound interface device associated with said first processor, said first inbound interface device receiving incoming packets and having a first input buffer accessible by said first processor, said first input buffer maintaining a queue of the packets received on said first inbound interface device;

a second inbound interface device associated with said second processor, said second inbound interface device receiving incoming packets and having a second input buffer accessible for reading by said second processor, said second input buffer maintaining a queue of the packets received on said second inbound interface device;

an outbound interface device associated with said second processor, said outbound interface receiving packets output from said second processor and transmitting said packets therefrom; and

a task queue accessible for reading by said second processor, said task queue receiving packets output from at least said first processor, the packets in said task queue being transmitted from said outbound interface device.

4. A method for operating a symmetric multiprocessor system including a first processor and a second processor for executing a multi-threaded process on packets, an inbound interface device associated with said first processor, a first outbound interface device associated with said first processor, a second outbound interface device associated with said second processor, and a task queue associated with said second processor, said method comprising:

receiving incoming packets on said first inbound interface device;

maintaining a queue of incoming packets received on said first inbound interface device in an input buffer;

requesting a buffer packet from said queue of packets in said input buffer;

executing a first process thread on said buffer packet;

sending said buffer packet processed by said first process thread to said task queue when said buffer packet is to be transmitted from said second outbound interface device; and

outputting said buffer requested packet processed by said first process thread to said first outbound interface device when said buffer packet is to be transmitted from said first outbound interface device.

5. The method as defined in claim 4, further comprising:

requesting a task packet from said task queue;

executing a second process thread on said task packet; and

outputting said task packet processed by said second thread to said second outbound interface device when said task packet is to be transmitted from said second outbound interface device.

6. A method for operating a symmetric multiprocessor system including a first processor and a second processor for executing a multi-threaded process on packets, a first inbound interface device associated with said first processor, a second inbound interface device associated with said second processor, an outbound interface device associated with said second processor, and a task queue associated with said second processor, said method comprising:

receiving incoming packets on said first inbound interface device;

maintaining a queue of incoming packets received on said first inbound interface device in a first input buffer;

requesting a first input buffer packet from said queue of packets in said first input buffer;

executing a first process thread on said first input buffer packet;

sending said first input buffer packet processed by said first process thread to said task queue when said first input buffer packet is to be transmitted from said outbound interface device;

requesting a task packet from said task queue;

executing a second process thread on said task packet; and

outputting said task packet processed by said second thread to said outbound interface device when said task packet is to be transmitted from said outbound interface device.

7. The method as defined in claim 6, further comprising:

receiving incoming packets on said second inbound interface device;

maintaining a queue of incoming packets received on said second inbound interface device in a second input buffer;

requesting a second input buffer packet from said queue of packets in said second input buffer;

executing a third process thread on said second input buffer packet; and

sending said second input buffer packet processed by said third process thread to said task queue when said second input buffer packet is to be transmitted from said outbound interface device.