Platform and method for supporting hibernate operations

• US 7,000,102 B2
• Filed: 06/29/2001
• Issued: 02/14/2006
• Est. Priority Date: 06/29/2001
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kumar, Mohan J., Kaushik, Shivnandan D., Rankin, Linda J., Crossland, James B., O'Shea, David J.
• Primary Examiner(s): Du, Thuan
• Application Number:
  US09/895,580
• Publication Number:
  US 20030018923A1
• Time in Patent Office: 1,691 Days
• Field of Search: 713/1, 713/2, 713/300, 713/323, 713/320, 713/324, 713/100, 710/260
• US Class Current: 713/2
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake

Abstract

One aspect of the invention relates to a method for supporting hibernation despite the presence of hot-plugged nodes and non-deterministic boot operations. The method comprises invoking a management interrupt in response to a Hibernate request. The management interrupt is used to obtain and store platform configuration information into a non-volatile storage location. The platform configuration information includes data to indicate whether a next boot sequence for a platform occurs as a deterministic boot sequence or a non-deterministic boot sequence as well as a boot node identifier and a listing of an order in which processors of the platform are initialized.

Claims

1. A method comprising:

invoking a management interrupt in response to a Hibernate request; and

storing platform configuration information into a non-volatile storage location, the platform configuration information including data to indicate whether a next boot sequence for a platform occurs as a deterministic boot sequence or a non-deterministic boot sequence where an order of processor initialization for the platform after hibernation differs from an order of processor initialization for the platform for a boot sequence, the non-deterministic boot sequence further uses a boot strap processor that differs from a processor that conducted a boot sequence prior to placing the platform into the Hibernate state.

2. The method of claim 1 further comprising storing a boot image of a platform including a first hot-plug processor substrate and a second hot-plug processor substrate.

3. The method of claim 2 further comprising placing the platform into a Hibernate state.

4. The method of claim 3, wherein the deterministic boot sequence uses a boot strap processor that conducted a boot sequence prior to placing the platform into the Hibernate state.

5. The method of claim 3 further comprising:

exiting from the Hibernate state by checking the platform configuration information to determine if a current boot sequence is a deterministic boot sequence and if so, using a boot strap processor that conducted a boot sequence prior to placing the platform into the Hibernate state.

6. The method of claim 2, wherein the platform configuration information further includes a boot node identifier and information as to an order of initialization of processors employed on the first processor substrate and the second processor substrate.

7. The method of claim 1, wherein prior to invoking of the management interrupt, the method further comprising making a function call to a Prepare to Sleep (_PTS) control method that invokes the management interrupt.

8. A software stored in platform readable medium executed by at least one processor within a platform, the software comprising:

a first software module to invoke a management interrupt in response to a Hibernate request;

a second software module to store platform configuration information into a non-volatile storage location, the platform configuration information including data to indicate whether a next boot sequence for a platform occurs as a deterministic boot sequence or a non-deterministic boot sequence where an order of processor initialization for the platform after hibernation differs from an order of processor initialization for the platform for a boot sequence prior to the hibernation, the non-deterministic boot sequence uses a boot strap processor, differing from a processor that conducted a boot sequence prior to placing the platform into a Hibernate state, to control the next boot sequence; and

a third software module to place the platform into the Hibernate state.

9. The software of claim 8 further comprising a third software module to initiate a function call to a Prepare to Sleep (_PTS) control method that, in turn, invokes the management interrupt.

10. The software of claim 8 further comprising:

a fourth software module to exit from the Hibernate state by checking the platform configuration information to determine if a current boot sequence is a deterministic boot sequence and if so, using a boot strap processor that conducted a boot sequence prior to placing the platform into the Hibernate state to control the current boot sequence.

11. The software of claim 8, wherein the platform configuration information further includes a boot node identifier and information as to an order of initialization of processors employed on the platform.

12. A platform comprising:

a plurality of hot-plug processor substrates collectively having a plurality of processors, one of the plurality of processors to request the platform to enter into a Hibernate state; and

an input/output (I/O) substrate including a non-volatile memory, the non-volatile memory being loaded with platform configuration information including data to indicate whether a next boot sequence for a platform occurs as a deterministic boot sequence or a non-deterministic boot sequence prior to entering the Hibernate state, the non-deterministic boot sequence is where an order of initialization of the plurality of processors after hibernation during the next boot sequence differs from an order of initialization of the plurality of processors for a boot sequence prior to the platform entering the Hibernate state, the non-deterministic boot sequence further uses a boot strap processor, differing from the one of the plurality of processors to request the platform to enter into the Hibernate state, to conduct the boot sequence prior to placing the platform into a Hibernate state, to control the current boot sequence.

13. The platform of claim 12, wherein the non-volatile memory further comprises a boot image of a platform loaded prior to entering the Hibernate state.

14. The platform of claim 12, wherein the non-volatile memory further comprises a Basic Input/Output System (BIOS).

15. The platform of claim 14, wherein, after power-on of the platform, the BIOS runs and checks the data associated with the platform configuration information to determine if a current boot sequence occurs as a deterministic boot sequence.

16. The platform of claim 15, wherein, in accordance with the deterministic boot sequence, a boot strap processor, being one of the plurality of processors that conducted a boot sequence prior to placing the platform into the Hibernate state, controls the current boot sequence.

17. The platform of claim 12, wherein the platform configuration information further includes a boot node identifier to uniquely identify at least each of the plurality of processor substrates and information as to an order of initialization of the plurality of processors.