Data processor and data processing system
First Claim
1. A data processor, comprising:
- a central processing unit which is capable of executing an instruction;
a clock pulse generator that enables frequency multiplication and frequency division operation to a clock and is capable of outputting a plurality of clock signals;
a mode control circuit;
a timer circuit; and
other circuit modules,wherein the data processor has a plurality of operation modes including a standby mode, a light standby mode, a sleep mode, and a program running mode,wherein in the program running mode, the central processing unit is capable of executing instructions,wherein in the sleep mode, the clock pulse generator operates the frequency multiplication and frequency division operation, stops supplying one of the clock signals to the central processing unit, and supplies the remaining clock signals to said other circuit modules,wherein in the standby mode, the clock pulse generator is made to stop operating, to stop supplying the clock signals to the central processing unit and said other circuit modules, andwherein in the light standby mode, the clock pulse generator operates the frequency multiplication and frequency division operation, and stops supplying the clock signals to said other circuit modules and the central processing unit,wherein the mode control circuit is capable of changing the data processor from the sleep mode to the light standby mode in response to a predetermined value by the timer circuit, andwherein the mode control circuit is capable of suppressing the counting in response to a direct memory access transfer request on the way to the counting of up to the predetermined value by the timer circuit.
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Accused Products
Abstract
This data processor can satisfy both requests of a fast transition from a low power consumption state to an operating state and low power consumption, and a data processor has a program running state, a standby mode, a light standby mode, and a sleep mode. In the sleep mode, the supply of a synchronizing clock signal to a central processing unit (CPU) is stopped and the synchronizing clock signal is supplied to other circuit modules. In the standby mode, the frequency multiplication and frequency operation of a clock pulse generator are suspended and the supply of the synchronizing clock signal to the CPU and other circuit modules is stopped. In the light standby mode, the frequency multiplication and frequency division operation of the clock pulse generator are enabled and the supply of the synchronizing clock signal to the CPU and other circuit modules is stopped. In the light standby mode, the transition of the CPU to an instruction executable state is faster than in the standby mode and the lower power consumption than in the sleep mode is obtained.
33 Citations
22 Claims
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1. A data processor, comprising:
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a central processing unit which is capable of executing an instruction; a clock pulse generator that enables frequency multiplication and frequency division operation to a clock and is capable of outputting a plurality of clock signals; a mode control circuit; a timer circuit; and other circuit modules, wherein the data processor has a plurality of operation modes including a standby mode, a light standby mode, a sleep mode, and a program running mode, wherein in the program running mode, the central processing unit is capable of executing instructions, wherein in the sleep mode, the clock pulse generator operates the frequency multiplication and frequency division operation, stops supplying one of the clock signals to the central processing unit, and supplies the remaining clock signals to said other circuit modules, wherein in the standby mode, the clock pulse generator is made to stop operating, to stop supplying the clock signals to the central processing unit and said other circuit modules, and wherein in the light standby mode, the clock pulse generator operates the frequency multiplication and frequency division operation, and stops supplying the clock signals to said other circuit modules and the central processing unit, wherein the mode control circuit is capable of changing the data processor from the sleep mode to the light standby mode in response to a predetermined value by the timer circuit, and wherein the mode control circuit is capable of suppressing the counting in response to a direct memory access transfer request on the way to the counting of up to the predetermined value by the timer circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A data processor, comprising:
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a central processing unit that can execute an instruction; a clock pulse generator that enables frequency multiplication and frequency operation on an input clock and outputs a plurality of clock signals;
other circuit modules; anda mode control circuit that controls settings of first and second modes included in said other circuit modules, wherein the data processor has a program running mode, a first mode, and a second mode, wherein in the program running mode, the central processing unit is capable of executing the instruction, wherein in the first mode, the clock pulse generator is stopped to supply the clock signals to the central processing unit, and the clock pulse generator supplies the clock signals to said other circuit modules, wherein in the second mode, the clock pulse generator operates the frequency multiplication and frequency division operation, and the clock pulse generator stops supplying the clock signals to the central processing unit and said other circuit modules, wherein the mode control circuit changes the first operation mode to the second operation mode when there is no operation instruction to the central processing unit until a predetermined lapse of time after the first mode is set, wherein the predetermined lapse of time is obtained by a counting operation of up to a predetermined value by a timer, wherein said other circuit modules include a direct memory access controller, wherein the timer initializes a counted value in response to a direct memory access transfer request to the direct memory access controller in the counting operations, wherein the mode control circuit is capable of suppressing the counting in response to a direct memory access transfer request on the way to the counting of up to the predetermined value by the timer. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A data processing system, comprising:
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a data processor including a central processing unit that can execute an instruction;
a clock pulse generator that enables frequency multiplication and frequency operation on an input clock and outputs a plurality of clock signals;
other circuit modules;
a mode control circuit that controls settings of first and second modes included in said other circuit modules; and
a timer circuit, the mode control circuit being capable of changing the data processor from the sleep mode to the light standby mode in response to a predetermined value by the timer circuit;a memory which is accessed by the central processing unit of the data processor; and a circuit that requests an interrupt to the data processor, wherein the data processor has a program running mode, a first mode, and a second mode, wherein in the program running mode, the central processing unit is capable of executing the instruction, wherein in the first mode, the clock pulse generator is stopped to supply the clock signals to the central processing unit, and the clock pulse generator supplies the clock signals to said other circuit modules, wherein in the second mode, the clock pulse generator operates the frequency multiplication and frequency division operation, and the clock pulse generator stops supplying the clock signals to the central processing unit and said other circuit modules, wherein the mode control circuit changes the first operation mode to the second operation mode when there is no operation instruction to the central processing unit until a predetermined lapse of time after the first mode is set, and wherein the mode control circuit is capable of suppressing the counting in response to a direct memory access transfer request on the way to the counting of up to the predetermined value by the timer circuit. - View Dependent Claims (21)
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22. A data processing system, comprising:
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a data processor including a central processing unit that can execute an instruction;
a clock pulse generator that enables frequency multiplication and frequency operation on an input clock and outputs a plurality of clock signals;
other circuit modules;
a mode control circuit that controls settings of first and second modes included in said other circuit modules; and
a timer circuit, the mode control circuit being capable of changing the data processor from the sleep mode to the light standby mode in response to a predetermined value by the timer circuit;a memory which is accessed by the central processing unit of the data processor can access; and a circuit that requests an interrupt to the data processor, wherein the data processor has a program running mode, a first mode, and a second mode, wherein in the program running mode, the central processing unit is capable of executing the instruction, wherein in the first mode, the clock pulse generator is stopped to supply the clock signals to the central processing unit, and the clock pulse generator supplies the clock signals to said other circuit modules, wherein in the second mode, the clock pulse generator operates the frequency multiplication and frequency division operation, and the clock pulse generator stops supplying the clock signals to the central processing unit and said other circuit modules, wherein the mode control circuit changes the first operation mode to the second operation mode when there is no operation instruction to the central processing unit until a predetermined lapse of time after the first mode is set, wherein the mode control circuit includes a control register, and sets the first mode in response to a first state of the control register when a predetermined instruction is executed by the central processing unit, and sets the second mode in response to a second state of the control register when a predetermined instruction is executed by the central processing unit, and wherein the mode control circuit is capable of suppressing the counting in response to a direct memory access transfer request on the way to the counting of up to the predetermined value by the timer circuit.
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Specification