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Data processor and data processing system

  • US 7,000,140 B2
  • Filed: 11/27/2001
  • Issued: 02/14/2006
  • Est. Priority Date: 11/29/2000
  • Status: Expired due to Fees
First Claim
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1. A data processor, comprising:

  • a central processing unit which is capable of executing an instruction;

    a clock pulse generator that enables frequency multiplication and frequency division operation to a clock and is capable of outputting a plurality of clock signals;

    a mode control circuit;

    a timer circuit; and

    other circuit modules,wherein the data processor has a plurality of operation modes including a standby mode, a light standby mode, a sleep mode, and a program running mode,wherein in the program running mode, the central processing unit is capable of executing instructions,wherein in the sleep mode, the clock pulse generator operates the frequency multiplication and frequency division operation, stops supplying one of the clock signals to the central processing unit, and supplies the remaining clock signals to said other circuit modules,wherein in the standby mode, the clock pulse generator is made to stop operating, to stop supplying the clock signals to the central processing unit and said other circuit modules, andwherein in the light standby mode, the clock pulse generator operates the frequency multiplication and frequency division operation, and stops supplying the clock signals to said other circuit modules and the central processing unit,wherein the mode control circuit is capable of changing the data processor from the sleep mode to the light standby mode in response to a predetermined value by the timer circuit, andwherein the mode control circuit is capable of suppressing the counting in response to a direct memory access transfer request on the way to the counting of up to the predetermined value by the timer circuit.

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