Power loss memory back-up

• US 7,000,146 B2
• Filed: 05/31/2001
• Issued: 02/14/2006
• Est. Priority Date: 05/31/2001
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mackey, Richard P., Bissessur, Sailesh, Warren, James D., Luckett, Richard P.
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): PUENTE, EMERSON C
• Application Number:
  US09/872,872
• Publication Number:
  US 20020184574A1
• Time in Patent Office: 1,720 Days
• Field of Search: 714/22, 714/24, 714/47, 713/340
• US Class Current: 714/22
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24

Abstract

A memory system provides one or more control signals for configuring and controlling a memory sub-system during a power failure or system reset. A power delay circuit and a power fail controller cooperate to quickly place the memory system in a retention state in the event a power failure event is detected. The power delay circuit detects either a reset signal or power failure to initiate the memory retention state. The power delay circuit and power fail controller ensure the memory system is initialized prior to entering the retention state.

Claims

1. A system comprising:

a voltage monitor to monitor a voltage of the system and to transmit a voltage monitor signal if the voltage falls below a predetermined threshold;

a power delay circuit to transmit a power delay signal in response to receiving a voltage monitor signal and to transmit a reset signal if the voltage monitor signal indicates a reset condition or in response to an external event reset signal;

a memory sub-system to store digital data and having a self-refresh circuit, the self-refresh circuit causing the memory sub-system to enter into a self-refresh sequence; and

a memory controller to control and configure the memory sub-system, the memory controller having a power fail controller to receive a power delay signal or a reset signal from the power delay circuit, the power controller asserting a system reset signal and sending two configuration signals in response to the power delay signal or external event reset signal, the configuration signals indicating whether the external event reset signal was detected for at least a predetermined amount of time and at least one of a power failure or an external reset event is detected.

2. The system of claim 1, wherein the memory controller further comprises a state machine to receive the system reset signal and the configuration signals and to direct the memory sub-system into a self-refresh state based on the system reset signal and the configuration signals.

3. The system of claim 1, further comprising means for generating an external event signal.

4. The system of claim 1, wherein the power fail controller prevents the self-refresh sequence from executing when the system is not configured.

5. A system comprising:

a voltage monitor to monitor a voltage of the system and to transmit a voltage monitor signal if the voltage falls below a predetermined threshold;

means for transmitting a power delay signal and a reset signal, wherein the power delay signal is transmitted in response to receiving a voltage monitor signal and the reset signal is transmitted if the voltage monitor signal indicates a reset condition or in response to an external event reset signal;

a memory sub-system to store digital data and having a self-refresh circuit, the self-refresh circuit causing the memory sub-system to enter into a self-refresh sequence; and

a memory controller to control and configure the memory sub-system, the memory controller having a power fail controller to receive a power delay signal or a reset signal from the means for transmitting a power delay signal and a reset signal, the power controller asserting a system reset signal and sending two configuration signals in response to the power delay signal or external event reset signal, the configuration signals indicating whether the external event reset signal was detected for at least a predetermined amount of time and at least one of a power failure or an external reset event is detected.

6. The system of claim 5, wherein the memory controller further comprises a state machine to receive the system reset signal and the configuration signals and to direct the memory sub-system into a self-refresh state based on the system reset signal and the configuration signals.

7. The system of claim 5, further comprising means for generating an external event signal.

8. The system of claim 5, wherein the power fail controller prevents the self-refresh sequence from executing when the system is not configured.

9. A system comprising:

means for monitoring a voltage of the system and to transmit a voltage monitor signal if the voltage falls below a predetermined threshold;

a power delay circuit to transmit a power delay signal in response to receiving a voltage monitor signal and to transmit a reset signal if the voltage monitor signal indicates a reset condition or in response to an external event reset signal;

a memory sub-system to store digital data and having a self-refresh circuit, the self-refresh circuit causing the memory sub-system to enter into a self-refresh sequence; and

means for controlling and configuring the memory sub-system, the means for controlling and configuring the memory sub-system having a power fail controller to receive a power delay signal or a reset signal from the power delay circuit, the power controller asserting a system reset signal and sending two configuration signals in response to the power delay signal or external event reset signal, the configuration signals indicating whether the external event reset signal was detected for at least a predetermined amount of time and at least one of a power failure or an external reset event is detected.

10. The system of claim 9, wherein the means for controlling and configuring the memory sub-system further comprises a state machine to receive the system reset signal and the configuration signals and to direct the memory sub-system into a self-refresh state based on the system reset signal and the configuration signals.

11. The system of claim 9, further comprising means for generating an external event signal.

12. The system of claim 9, wherein the power fail controller prevents the self-refresh sequence from executing when the system is not configured.