Power loss memory back-up
First Claim
Patent Images
1. A system comprising:
- a voltage monitor to monitor a voltage of the system and to transmit a voltage monitor signal if the voltage falls below a predetermined threshold;
a power delay circuit to transmit a power delay signal in response to receiving a voltage monitor signal and to transmit a reset signal if the voltage monitor signal indicates a reset condition or in response to an external event reset signal;
a memory sub-system to store digital data and having a self-refresh circuit, the self-refresh circuit causing the memory sub-system to enter into a self-refresh sequence; and
a memory controller to control and configure the memory sub-system, the memory controller having a power fail controller to receive a power delay signal or a reset signal from the power delay circuit, the power controller asserting a system reset signal and sending two configuration signals in response to the power delay signal or external event reset signal, the configuration signals indicating whether the external event reset signal was detected for at least a predetermined amount of time and at least one of a power failure or an external reset event is detected.
1 Assignment
0 Petitions
Accused Products
Abstract
A memory system provides one or more control signals for configuring and controlling a memory sub-system during a power failure or system reset. A power delay circuit and a power fail controller cooperate to quickly place the memory system in a retention state in the event a power failure event is detected. The power delay circuit detects either a reset signal or power failure to initiate the memory retention state. The power delay circuit and power fail controller ensure the memory system is initialized prior to entering the retention state.
-
Citations
12 Claims
-
1. A system comprising:
-
a voltage monitor to monitor a voltage of the system and to transmit a voltage monitor signal if the voltage falls below a predetermined threshold; a power delay circuit to transmit a power delay signal in response to receiving a voltage monitor signal and to transmit a reset signal if the voltage monitor signal indicates a reset condition or in response to an external event reset signal; a memory sub-system to store digital data and having a self-refresh circuit, the self-refresh circuit causing the memory sub-system to enter into a self-refresh sequence; and a memory controller to control and configure the memory sub-system, the memory controller having a power fail controller to receive a power delay signal or a reset signal from the power delay circuit, the power controller asserting a system reset signal and sending two configuration signals in response to the power delay signal or external event reset signal, the configuration signals indicating whether the external event reset signal was detected for at least a predetermined amount of time and at least one of a power failure or an external reset event is detected. - View Dependent Claims (2, 3, 4)
-
-
5. A system comprising:
-
a voltage monitor to monitor a voltage of the system and to transmit a voltage monitor signal if the voltage falls below a predetermined threshold; means for transmitting a power delay signal and a reset signal, wherein the power delay signal is transmitted in response to receiving a voltage monitor signal and the reset signal is transmitted if the voltage monitor signal indicates a reset condition or in response to an external event reset signal; a memory sub-system to store digital data and having a self-refresh circuit, the self-refresh circuit causing the memory sub-system to enter into a self-refresh sequence; and a memory controller to control and configure the memory sub-system, the memory controller having a power fail controller to receive a power delay signal or a reset signal from the means for transmitting a power delay signal and a reset signal, the power controller asserting a system reset signal and sending two configuration signals in response to the power delay signal or external event reset signal, the configuration signals indicating whether the external event reset signal was detected for at least a predetermined amount of time and at least one of a power failure or an external reset event is detected. - View Dependent Claims (6, 7, 8)
-
-
9. A system comprising:
-
means for monitoring a voltage of the system and to transmit a voltage monitor signal if the voltage falls below a predetermined threshold; a power delay circuit to transmit a power delay signal in response to receiving a voltage monitor signal and to transmit a reset signal if the voltage monitor signal indicates a reset condition or in response to an external event reset signal; a memory sub-system to store digital data and having a self-refresh circuit, the self-refresh circuit causing the memory sub-system to enter into a self-refresh sequence; and means for controlling and configuring the memory sub-system, the means for controlling and configuring the memory sub-system having a power fail controller to receive a power delay signal or a reset signal from the power delay circuit, the power controller asserting a system reset signal and sending two configuration signals in response to the power delay signal or external event reset signal, the configuration signals indicating whether the external event reset signal was detected for at least a predetermined amount of time and at least one of a power failure or an external reset event is detected. - View Dependent Claims (10, 11, 12)
-
Specification