Optimized buffering for JTAG boundary scan nets

• US 7,000,163 B1
• Filed: 02/25/2002
• Issued: 02/14/2006
• Est. Priority Date: 02/25/2002
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Dirks, Juergen, Mbouombouo, Benjamin, Li, Weidan, Lahner, Juergen K., Boluki, Human, Johanterwage, Ludger F.
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Trimmings, John P.
• Application Number:
  US10/082,737
• Time in Patent Office: 1,450 Days
• Field of Search: 714/727, 714/726, 714/729, 716/16
• US Class Current: 714/727
• CPC Class Codes: G01R 31/318541 Scan latches or cell details
• CPC Class Codes: G01R 31/318572 Input/Output interfaces

Abstract

An apparatus comprising one or more groups of boundary scan cells, one or more group buffers, one or more repeater buffers and a controller. The group buffers may be coupled to each of the groups of boundary scan cells. The repeater buffers may be coupled in series with the group buffers. The controller may be coupled to the groups of boundary scan cells through the group buffers and the repeater buffers. The apparatus may be configured to buffer the groups of boundary scan cells to reflect an order of I/Os around the apparatus.

Claims

1. An apparatus comprising:

one or more groups of boundary scan cells;

one or more group buffers coupled to each of said groups of boundary scan cells;

one or more repeater buffers coupled in series with said group buffers;

a controller coupled to said groups of boundary scan cells through said group buffers and said repeater buffers, wherein (i) said apparatus is configured to buffer said groups of boundary scan cells to reflect an order of I/Os around said apparatus and (ii) said groups of boundary scan cells are routed within an I/O portion of said apparatus to avoid routing through an interior portion of said apparatus to keep said interior portion free for functional routing;

one or more flip flops each configured to provide a scan enable output; and

a scan enable signal configured to control a scan connection between each of said flip flops.

2. The apparatus according to claim 1, wherein said groups of boundary scan cells comprise a scan chain.

3. The apparatus according to claim 2, wherein said repeater buffers are configured to eliminate skew at the beginning pins and end pins of the scan chain.

4. The apparatus according to claim 1, wherein said apparatus further comprises:

one or more boundary scan control nets configured to control said groups of boundary scan cells.

5. The apparatus according to claim 1, wherein each boundary scan cell of said groups of boundary scan cells are implemented within an I/O cell.

6. The apparatus according to claim 1, wherein said apparatus comprises a clock chain in a first direction and a data path in an opposite direction of said first direction.

7. An apparatus comprising:

means for implementing one or more groups of boundary scan cells;

means for implementing one or more group buffers coupled to each one of said groups of boundary scan cells;

means for implementing one or more repeater buffers coupled in series with said group buffers; and

means for controlling coupled to said groups of boundary scan cells through said group buffers and said repeater buffers;

means for buffering said groups of boundary scan cells to reflect an order of I/Os around said apparatus, wherein said groups of boundary scan cells are routed within an I/O portion of said apparatus to avoid routing through an interior portion of said apparatus to keep said interior portion free for functional routing;

means for providing a scan enable output; and

means for controlling a scan connection between one or more flip flops.

8. A method for optimizing buffers for JTAG boundary scan nets, comprising the steps of:

(A) reading a netlist;

(B) reading an I/O order list;

(C) defining a number of I/Os per groups;

(D) determining if a last I/O is connected;

(E) writing a final netlist; and

(F) determining if starting a new group is necessary.

9. The method according to claim 8, wherein step (D) further comprises:

splitting a net.

10. The method according to claim 9, wherein step (D) further comprises:

inserting a repeater buffer.

11. The method according to claim 10, wherein step (D) further comprises:

inserting a group buffer.

12. The method according to claim 8, wherein step (D) further comprises:

connecting a next I/O to a newest group buffer.

13. The method according to claim 8, further comprising the following step:

repeating step (D).

14. The method according to claim 8, wherein step (E) further comprises:

buffering said JTAG boundary scan nets to reflect the order of I/O cells around a circuit.

15. The method according to claim 8, wherein steps (E) further comprises:

providing boundary scan cell placement.

16. The method according to claim 8, wherein step (E) further comprises:

allowing optimum results to be obtained automatically.