Method of forming and using a hardmask for forming ferroelectric capacitors in a semiconductor device

• US 7,001,821 B2
• Filed: 11/10/2003
• Issued: 02/21/2006
• Est. Priority Date: 11/10/2003
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Taylor, Kelly J., Moise, Theodore S., Aggarwal, Sanjeev
• Primary Examiner(s): Le, Dung A.
• Application Number:
  US10/705,039
• Publication Number:
  US 20050101034A1
• Time in Patent Office: 834 Days
• Field of Search: 438/253, 438254-256, 438/3, 438/396, 438240-239
• US Class Current: 438/396
• CPC Class Codes: H01L 21/28568 the conductive layers comprising transition metals H01L21/28518 takes precedence
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 28/65 comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
• CPC Class Codes: H01L 28/75 comprising two or more layers, e.g. comprising a barrier layer and a metal layer
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode and ferroelectric layers are etched to define a ferroelectric capacitor stack.

Claims

1. A method of fabricating a ferroelectric capacitor in a semiconductor device, the method comprising:

forming a lower electrode material above a first contact;

forming a ferroelectric material above the lower electrode material;

forming an upper electrode material above the ferroelectric material;

forming a strontium tantalum oxide hardmask above the upper electrode material; and

etching portions of the upper electrode material, the ferroelectric material, and the lower electrode material using the strontium tantalum oxide hardmask to form a ferroelectric capacitor.

2. The method of claim 1, wherein forming the strontium tantalum oxide hardmask comprises forming a strontium tantalum oxide layer above the upper electrode material, forming a capacitor stack etch mask over the strontium tantalum oxide layer, and etching portions of the strontium tantalum oxide layer to form the strontium tantalum oxide hardmask.

3. The method of claim 2, wherein etching portions of the strontium tantalum oxide layer comprises reactive ion etching (RIE).

4. The method of claim 1, wherein etching portions of the upper electrode material, the ferroelectric material, and the lower electrode material comprises reactive ion etching (RIE).

5. The method of claim 1, wherein etching portions of the upper electrode material, the ferroelectric material, and the lower electrode material comprises reactive ion etching (RIE).

6. The method of claim 1, wherein forming the ferroelectric material comprises forming lead zirconate titanate (PZT) or strontium bismuth tantalate (SBT).

7. The method of claim 1, further comprising forming a first hardmask layer over the upper electrode material, forming the strontium tantalum oxide hardmask over the first hardmask layer, and forming a third hardmask layer over the strontium tantalum oxide hardmask, and wherein the first and third hardmask layers comprise a material having titanium and aluminum content or chromium nitride.