Self-aligned structure with unique erasing gate in split gate flash
First Claim
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1. A split-gate flash memory device comprising:
- a floating gate overlying a substrate;
a control gate overlying said substrate, comprising at least one sidewall laterally adjacent to said floating gate, and a top surface; and
an erase gate laterally adjacent to said floating gate and overlying said top surface of said control gate wherein said erase gate is between a sidewall spacer and said floating gate.
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Abstract
A split-gate flash memory device. The device includes a floating gate, a control gate, and an erase gate. The floating gate is overlying a substrate. The control gate is laterally adjacent to the floating gate and overlying the substrate. The erase gate is laterally adjacent to the floating gate and overlying the control gate, in which the erase gate is between a sidewall spacer and the floating gate.
15 Citations
21 Claims
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1. A split-gate flash memory device comprising:
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a floating gate overlying a substrate; a control gate overlying said substrate, comprising at least one sidewall laterally adjacent to said floating gate, and a top surface; and an erase gate laterally adjacent to said floating gate and overlying said top surface of said control gate wherein said erase gate is between a sidewall spacer and said floating gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A split-gate flash memory device comprising:
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a floating gate overlying a substrate; a structural dielectric layer overlying the floating gate; a control gate laterally adjacent to the floating gate and overlying the substrate; a sidewall spacer overlying the control gate; an erase gate surrounded by an erase dielectric layer, overlying the control gate and between the sidewall spacer and the structural dielectric layer; a source region in the substrate adjacent to the floating gate; and a drain region in the substrate outside of the control gate. - View Dependent Claims (14, 15, 16, 17)
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18. A split-gate flash memory device comprising:
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a substrate having a source region and a drain region; a source plug disposed on the source region; a floating gate overlying the substrate adjacent to the source region and insulated from the substrate; a structural dielectric layer overlying the floating gate; a control gate laterally adjacent to the floating gate and overlying the substrate, wherein the control gate is insulated from the floating gate and the substrate by a control dielectric layer; a sidewall spacer overlying the control gate and separated from the structural dielectric layer by a gap; an erase gate disposed in the gap and surrounded by an erase dielectric layer; and a metal bit line contacting the drain region. - View Dependent Claims (19, 20, 21)
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Specification
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Current AssigneeTaiwan Semiconductor Manufacturing Company Limited
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Original AssigneeTaiwan Semiconductor Manufacturing Company Limited
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InventorsHsieh, Chia-Ta
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Primary Examiner(s)Nhu, David
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Application NumberUS10/877,677Publication NumberTime in Patent Office606 DaysField of Search257/296, 257/68, 257/314, 257/315, 257/316, 257/318, 257/319, 257/320US Class Current257/296CPC Class CodesH10B 41/30 characterised by the memory...H10B 69/00 Erasable-and-programmable R...
