Super-junction semiconductor device and method of manufacturing the same

• US 7,002,205 B2
• Filed: 12/12/2003
• Issued: 02/21/2006
• Est. Priority Date: 02/09/2000
• Status: Expired due to Term

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Device Technology Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Sato, Takahiro, Onishi, Yasuhiko, Iwamoto, Susumu, Nagaoka, Tatsuji, Ueno, Katsunori, Fujihira, Tatsuhiko
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Warren, Matthew E.
• Application Number:
  US10/735,501
• Publication Number:
  US 20040124465A1
• Time in Patent Office: 802 Days
• Field of Search: 257/328, 257/329, 257/339, 257/342, 257/401, 257/409, 257/490, 257/494, 257/495
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted. Thus, the breakdown voltage of breakdown withstanding region is higher than the breakdown voltage of drain drift region.

Claims

1. A semiconductor device comprising:

a semiconductor chip having a first major surface and a second major surface opposing the first major surface;

an active region on a side of the first major surface;

a layer of a first conductivity type on a side of the second major surface;

a first main electrode electrically connected to the active region;

a second main electrode electrically connected to the layer of the first conductivity type;

a drain drift region between the active region and the layer of the first conductivity type, the drain drift region providing a vertical drift current path in the ON-state of the device and being depleted in the OFF-state of the device; and

a breakdown withstanding region around the drain drift region and between the first major surface and the layer of the first conductivity type,

wherein the breakdown withstanding region substantially does not provide any current path in the ON-state of the device and is depleted in the OFF-state of the device,

wherein the breakdown withstanding region comprises an alternating conductivity type layer comprising first regions of the first conductivity type and second regions of a second conductivity type arranged alternately with each other,

wherein the drain drift region comprises an alternating conductivity type layer comprising vertical drift current path regions of the first conductivity type and vertical partition regions of the second conductivity type, the drift current path regions and the partition regions extending in the thickness direction of the semiconductor chip, and the drift current path regions and the partition regions being arranged alternately with each other,

wherein the alternating conductivity type layer of the drain drift region comprises a laminate formed of a plurality of a pair of the drift current path region and the partition region, and the alternating conductivity type layer of the breakdown withstanding region comprises a laminate formed of a plurality of a pair of the first region and the second region,

wherein the pitch of repeating in the breakdown withstanding region, at which the pair of the first region and the second region is repeated, is narrower than the pitch of repeating in the drain drift region, at which the pair of the drift current path region and the partition region is repeated, and

wherein the alternating conductivity type layer of the breakdown withstanding region comprises a first alternating conductivity type section including the first regions and the second regions, the boundary planes therebetween extend almost in parallel to the boundary planes between the drift current path regions and the partition regions of the drain drift region, and a second alternating conductivity type section including the first regions and the second regions, the boundary planes therebetween extend in perpendicular to the boundary planes between the drift current path regions and the partition regions of the drain region.

2. The semiconductor device according to claim 1, wherein a plane, on which the end faces of the first regions and the second regions of the first alternating conductivity type section are arranged alternately, is bonded to the plane, on which the end faces of the drift current regions and the partition regions of the drain drift region are arranged alternately.

3. The semiconductor device according to claim 1, wherein the alternating conductivity type layer of the breakdown withstanding region further comprises a third alternating conductivity type section in the corner portion of the breakdown withstanding region defined by the first alternating conductivity type section and the second alternating conductivity type section, the third alternating conductivity type section including the first regions and the second regions extending in parallel to the first regions and the second regions of the first alternating conductivity type section or the second alternating conductivity type section.

4. The semiconductor device according to claim 1, wherein a plane, on which end faces of the first regions and the second regions of the first alternating conductivity type section or the second alternating conductivity type section are arranged alternately, is bonded to a boundary plane of the innermost second region of the second alternating conductivity type section or the first alternating conductivity type section.