Floating entrance guard for preventing electrical short circuits

• US 7,002,215 B1
• Filed: 09/30/2002
• Issued: 02/21/2006
• Est. Priority Date: 09/30/2002
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: PTS Corporation
• Inventors: Miller, David
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Erdem, Fazli
• Application Number:
  US10/262,404
• Time in Patent Office: 1,240 Days
• Field of Search: 257/355, 257/522, 257/254, 257/354, 257/356, 257/691, 257/758, 257/662, 257/664, 257/770, 257/776, 438/53, 438/54, 438/106, 438/108, 438/19, 438/125, 438/622, 438/652, 438/666
• US Class Current: 257/355
• CPC Class Codes: B81B 7/0012 Protection against reverse engineering, unauthorised use, use in unintended manner, wrong insertion or pin assignment

Abstract

Methods and apparatuses are provided for protecting an interconnect line in a microelectromechanical system. The interconnect line is disposed over a substrate for conducting electrical signals, such as from a bonding pad to a mechanical component to effect movement as desired of the mechanical component. A first protective covering is disposed over a first portion of the interconnect line and a second protective covering is disposed over a second portion of the interconnect line. The first protective covering is provided in electrical communication with the substrate and the second protective covering is electrically isolated from the substrate.

Claims

1. A method for protecting an interconnect line disposed over a substrate to conduct electrical signals in a microelectromechanical system, the method comprising:

forming a first protective covering over a first portion of the interconnect line, wherein the first protective covering is in electrical communication with the substrate; and

forming a second protective covering over a second portion of the interconnect line, wherein the second protective covering is electrically isolated from the substrate,

wherein the interconnect line and at least one of the first and second protective coverings are separated only by atmosphere.

2. The method recited in claim 1 wherein the first protective covering and the interconnect line are separated only by atmosphere.

3. The method recited in claim 1 wherein the second protective covering and the interconnect line are separated only by atmosphere.

4. The method recited in claim 1 further comprising forming an electrically insulative barrier layer between the interconnect line and the substrate, wherein the barrier layer includes a first opening through which the first protective covering communicates electrically with the substrate.

5. The method recited in claim 4 wherein the barrier layer includes a second opening through which the first protective covering communicates electrically with the substrate, whereby an equipotential ring is formed around the interconnect line.

6. The method recited in claim 1 wherein the first and second protective coverings comprise polysilicon.

7. The method recited in claim 1 further comprising forming a third protective covering over a third portion of the interconnect line, wherein the third protective covering is electrically isolated from the substrate.

8. The method recited in claim 7 wherein the first protective covering is positioned longitudinally along the interconnect line between the second and third protective coverings.

9. The method recited in claim 8 further comprising:

forming a first protective jacket over a gap between the first and second protective coverings; and

forming a second protective jacket over a gap between the first and third protective coverings.

10. The method recited in claim 1 wherein a longitudinal end region of the second protective covering has a smaller height above the interconnect line than a central region of the second protective covering.

11. The method recited in claim 1 wherein longitudinal end regions of the second protective covering have smaller heights above the interconnect line than a central region of the second protective covering.

12. The method recited in claim 1 further comprising forming a protective jacket over a gap between the first and second protective coverings.

13. An interconnect shield for protecting an interconnect line disposed over a substrate to conduct electrical signals in a microelectromechanical system, the interconnect shield comprising:

a first protective covering disposed over a first portion of the interconnect line, wherein the first protective covering is in electrical communication with the substrate; and

a second protective covering disposed over a second portion of the interconnect line, wherein the second protective covering is electrically isolated from the substrate, wherein the interconnect line and at least one of the first and second protective coverings are separated only by atmosphere.

14. The interconnect shield recited in claim 13 wherein the first protective covering and the interconnect line are separated only by atmosphere.

15. The interconnect shield recited in claim 13 wherein the second protective covering and the interconnect line are separated only by atmosphere.

16. The interconnect shield recited in claim 13 further comprising an electrically insulative barrier layer disposed between the interconnect line and the substrate, wherein the barrier layer includes a first opening through which the first protective covering communicates electrically with the substrate.

17. The interconnect shield recited in claim 16 wherein the barrier layer includes a second opening through which the first protective covering communicates electrically with the substrate, whereby an equipotential ring is formed around the interconnect line.

18. The interconnect shield recited in claim 13 wherein the first and second protective coverings comprise polysilicon.

19. The interconnect shield recited in claim 13 further comprising a third protective covering disposed over a third portion of the interconnect line, wherein the third protective covering is electrically isolated from the substrate.

20. The interconnect shield recited in claim 19 wherein the first protective covering is positioned longitudinally along the interconnect line between the second and third protective coverings.

21. The interconnect shield recited in claim 20 further comprising:

a first protective jacket disposed over a gap between the first and second protective coverings; and

a second protective jacked disposed over a gap between the first and third protective coverings.

22. The interconnect shield recited in claim 13 wherein a longitudinal end region of the second protective covering has a smaller height above the interconnect line than a central region of the second protective covering.

23. The interconnect shield recited in claim 13 wherein longitudinal end regions of the second protective covering have smaller heights above the interconnect line than a central region of the second protective covering.

24. The interconnect shield recited in claim 13 further comprising a protective jacket disposed over a gap between the first and second protective coverings.

25. A method for fabricating a microelectromechanical system, the method comprising:

forming a bonding pad over an electrically conductive substrate;

forming a mechanical component over the substrate, wherein the mechanical component is adapted to engage in movement relative to the substrate;

forming an electrically conductive interconnect line along a longitudinal line between the bonding pad and the mechanical component;

forming a first protective covering over a first portion of the interconnect line, wherein the first protective covering is electrically conductive and is in electrical communication with the substrate; and

forming a second protective covering over a second portion of the interconnect line, wherein the second protective covering is electrically isolated from the substrates

wherein the interconnect line and at least one of the first or second protective coverings are separated only by atmosphere.

26. The method recited in claim 25 further comprising forming an electrically insulative barrier layer between the interconnect line and the substrate.

27. The method recited in claim 25 further comprising electrically coupling the first protective covering with the substrate to configure an equipotential ring around the interconnect line.

28. The method recited in claim 27 further comprising electrically coupling the substrate with the bonding pad, whereby the equipotential ring comprises a ground ring.

29. The method recited in claim 25 further comprising forming a third protective covering over a third portion of the interconnect line, wherein the third protective covering is electrically isolated from the substrate and wherein the first protective covering is disposed along the longitudinal line between the second and third protective coverings.

30. The method recited in claim 25 wherein a longitudinal end region of the second protective covering has a smaller height above the interconnect line than a central region of the second protective covering.

31. The method recited in claim 25 further comprising forming a protective jacket over a gap between the first and second protective coverings.

32. A microelectromechanical device comprising:

an electrically conductive substrate;

a bonding pad disposed over the substrate;

a mechanical component disposed over the substrate, wherein the mechanical component is adapted to engage in movement relative to the substrate;

an electrically conductive interconnect line disposed over the substrate along a longitudinal line between the bonding pad and the mechanical component;

a first protective covering disposed over a first portion of the interconnect line, wherein the first protective covering is electrically conductive and is in electrical communication with the substrate; and

a second protective covering disposed over a second portion of the interconnect line, wherein the second protective covering is electrically isolated from the substrate

wherein the interconnect line and at least one of the first and second protective coverings are separated only by atmosphere.

33. The microelectromechanical device recited in claim 32 further comprising an electrically insulative barrier layer disposed between the interconnect line and the substrate.

34. The microelectromechanical device recited in claim 32 wherein the first protective covering is electrically coupled with the substrate to configure an equipotential ring around the interconnect line.

35. The microelectromechanical device recited in claim 34 wherein the substrate is electrically coupled with the bonding pad.

36. The microelectromechanical device recited in claim 32 further comprising a third protective covering disposed over a third portion of the interconnect line, wherein the third protective covering is electrically isolated from the substrate and wherein the first protective covering is disposed along the longitudinal line between the second and third protective coverings.

37. The microelectromechanical device recited in claim 32 wherein a longitudinal end region of the second protective covering has a smaller height above the interconnect line than a central region of the second protective covering.

38. The microelectromechanical device recited in claim 32 further comprising a protective jacket disposed over a gap between the first and second protective coverings.

39. An interconnect shield for protecting an interconnect line disposed over a substrate to conduct electrical signals in a microelectromechanical system, the interconnect shield comprising:

first protective means for covering a first portion of the interconnect line, wherein the first protective means is in electrical communication with the substrate; and

second protective means for covering a second portion of the interconnect line, wherein the second protective means is electrically isolated from the substrate, wherein the interconnect line and at least one of the first and second protective means are separated only by atmosphere.

40. The interconnect shield recited in claim 39 further comprising barrier means for electrically insulating the interconnect line from the substrate.

41. The interconnect shield recited in claim 39 wherein the first protective means is electrically coupled with the substrate to configure an equipotential ring around the interconnect line.

42. The interconnect shield recited in claim 39 further comprising third protective means for covering a third portion of the interconnect line, wherein the third protective means is electrically isolated from the substrate and wherein the first protective means is disposed between the second and third protective means.

43. The interconnect shield recited in claim 39 wherein a longitudinal end region of the second protective means has a smaller height above the interconnect line than a central region of the second protective means.

44. The interconnect shield recited in claim 39 further comprising fourth protective means for covering a gap between the first and second protective means.