Integrated semiconductor memory circuit and method of manufacturing the same

• US 7,002,222 B2
• Filed: 01/09/2004
• Issued: 02/21/2006
• Est. Priority Date: 01/10/2003
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Sommer, Michael Bernhard
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): Soward, Ida M.
• Application Number:
  US10/753,407
• Publication Number:
  US 20050029602A1
• Time in Patent Office: 774 Days
• Field of Search: 257/204, 257/338, 257/351, 257/357, 257/369, 257/371, 257/E27.064, 257/E27.067, 257/E27.084, 257/E27.108, 257/548, 257/549, 257/550
• US Class Current: 257/371
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

An integrated semiconductor circuit, having active components lying in mutually adjoining wells of a respective first and second conduction type, wherein the active components respectively are associated with substrate contacts lying in direct proximity to an edge bounding the mutually adjoining wells, is disclosed. Preferably, structures of the active components other than the contacts are arranged to lie further away from the edge and the circuit/layout structures are not mirror-symmetrical with respect to a center line of the circuit chip.

Claims

1. A semiconductor device comprising:

a plurality of wells of a first conduction type, each well formed in a substrate and containing a first set of active components and a first set of contacts associated with the first set of active components; and

a plurality of wells of a second conduction type, each well formed in a substrate and containing a second set of active components and a second set of contacts associated with the active components,

wherein the wells of the first conduction type share a mutually adjoining boundary with the wells of the second conduction type, the mutually adjoining boundary disposed within a border region, wherein a contamination zone due to implantation scattering during well implantation lies within the border region;

wherein the first set of contacts and second set of contacts lie in the border region near the mutually adjoining boundary, and

wherein the active components lie further away from the mutually adjoining boundary than do the first and second set of contacts.

2. The semiconductor device of claim 1, wherein the device comprises a memory chip.

3. The semiconductor device of claim 1, wherein the active components lie outside the border region.

4. The semiconductor device of claim 1, wherein the wells of the first conduction type and the wells of the second conduction type are arranged in a circuit layout structure that is not mirror-symmetrical with respect to a center line therein.

5. The semiconductor device of claim 4, wherein the wells of the first conduction type are p-type, and each include at least one n-channel FET fabricated thereon, and

wherein the wells of the second conduction type are n-type, and include at least one p-channel FET fabricated thereon.

6. A semiconductor chip comprising:

a plurality of pairs of wells, each pair including an n-type well adjacent to a p-type well, wherein a border region is defined along an edge where each n-well and p-well are mutually adjacent;

a set of contacts within each well arranged to lie within the border region; and

a set of active components within each well arranged to lie outside the border region;

wherein the arrangement of the pairs of wells is such that there is no mirror symmetry of the well location with respect to a line through the center of the chip; and

wherein a contamination zone due to implantation scattering during well implantation lies within the border region within each pair of wells.

7. The semiconductor chip of claim 6, wherein the semiconductor chip comprises a memory chip.

8. The semiconductor device of claim 7, wherein the memory chip comprises a DRAM chip.

9. The semiconductor device of claim 8, wherein the wells of the first conduction type and the wells of the second conduction type are arranged in a circuit layout structure that is not mirror-symmetrical with respect to a center line therein.

10. The semiconductor device of claim 9, wherein the wells of the first conduction type are p-type, and each include at least one n-channel FET fabricated thereon, and

wherein the wells of the second conduction type are n-type, and include at least one p-channel FET fabricated thereon.

11. The semiconductor chip of claim 7, wherein the semiconductor chip comprises a DRAM chip.

12. A semiconductor device comprising:

a plurality of pairs of wells, each pair including an n-type well adjacent to a p-type well, wherein a border region is defined along an edge where each n-well and p-well are mutually adjacent, wherein a contamination zone due to implantation scattering during well implantation lies within the border region within each pair of wells;

at least one contacts within each well arranged to lie within the border region; and

at least one active component within each well arranged to lie outside the border region.

13. The device of claim 12, wherein the semiconductor device comprises a memory chip.

14. The device of claim 13, wherein the semiconductor device comprises a DRAM chip.

15. The device of claim 12, wherein no active components lie within the border region within each well.

16. The device of claim 12, wherein the pairs of wells are arranged such that there is no mirror symmetry of the well location with respect to a line through the center of a region that includes the wells.