Moderate current 5V tolerant buffer using a 2.5 volt power supply

• US 7,002,372 B2
• Filed: 01/20/2004
• Issued: 02/21/2006
• Est. Priority Date: 01/20/2004
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Smooha, Yehuda, Morris, Bernard Lee, Huber, Carol Ann, Kothandaraman, Makeshwar
• Primary Examiner(s): Chang, Daniel D.
• Application Number:
  US10/759,162
• Publication Number:
  US 20050156628A1
• Time in Patent Office: 763 Days
• Field of Search: 326/80, 326/81, 326/82, 326/83, 326/86
• US Class Current: 326/81
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/018592 with a bidirectional operation

Abstract

A low voltage, 5V tolerant open drain output buffer having moderate current tolerance capabilities is formed with 3.3V technology using a nominal power supply of 2.5V or less. The buffer includes an inverter, a series connection of the current paths of three n-channel FET transistors, and a backgate bias generator. One terminal of the series connection of three transistors is connected to a PAD, and the other terminal of the lower transistor of the series is connected to ground. The bias generator is formed using two p-channel field effect transistors (FETs) that are cross-connected between VDD and the PAD. A gate of a central one of the three transistors is connected to the power supply. An output of the bias generator is connected to a gate of the upper transistor. The inventive buffer may be manufactured using standard 3.3V processes, but functions with a power supply of, e.g., 2.5V or 1.8V.

Claims

1. A low voltage, 5V tolerant buffer, comprising:

a series connection of at least three transistors, a terminal of an upper transistor in said series connection being connected to a PAD, and a terminal of a lower transistor of said series connection being connected to ground;

a bias generator, an output of said bias generator being connected to a gate of said upper transistor; and

an input stage driven by a node between said central transistor and said lower transistor;

wherein a gate of a central one of said series connection of three transistors is adapted to be connected to a power supply of no greater than 2.5V nominal; and

said buffer is a bi-directional buffer.

2. The low voltage, 5V tolerant buffer according to claim 1, wherein said bias generator comprises:

a series connection of two p-channel field effect transistors;

said series connection of said two transistors being connected between said power supply and said PAD.

3. The low voltage, 5V tolerant buffer according to claim 2, wherein:

a gate of one of said two transistors is adapted to be coupled to said PAD, and a gate of the other of said two transistors is adapted to be driven by said power supply.

4. The low voltage, 5V tolerant buffer according to claim 1, wherein:

said upper transistor, said lower transistor, and said central transistor are each an n-channel field effect transistor.

5. The low voltage, 5V tolerant buffer according to claim 1, wherein:

said buffer can reliably sink no more than about 16 milliamps of current.

6. The low voltage, 5V tolerant buffer according to claim 1, wherein:

said buffer is comprised in a SCSI bus.

7. The low voltage, 5V tolerant buffer according to claim 1, wherein:

said buffer is comprised in a PCI bus.

8. The low voltage, 5V tolerant buffer according to claim 1, wherein:

said buffer is comprised in a PCMCIA bus.

9. The low voltage, 5V tolerant buffer according to claim 1, further comprising:

an integrated circuit including said 5V tolerant buffer.

10. The low voltage, 5V tolerant buffer according to claim 1, wherein:

a channel width of at least one of said at least three transistors is at least 400 um.

11. The low voltage, 5V tolerant buffer according to claim 1, wherein:

said series connection of at least three transistors is a series connection of a current path of each of said at least three transistors.

12. The low voltage, 5V tolerant buffer according to claim 1, wherein:

each of said at least three transistors are a field effect transistor.

13. A method of providing a low voltage, 5V tolerant buffer, comprising:

providing a series connection of at least three transistors;

connecting an end of an upper transistor in said series connection to a PAD;

connecting an end of a lower transistor of said series connection to ground;

providing a bias voltage to a gate of said upper transistor, said bias voltage being based on a difference between a power supply voltage and a voltage at said PAD;

providing a power supply input to a gate of a central one of said series connection of three transistors; and

providing an input stage adapted to be driven by a node between said central transistor and said lower transistor.

14. The method of providing a low voltage, 5V tolerant buffer according to claim 13, further comprising:

providing a power supply voltage of no greater than 2.5V nominal.

15. The method or providing a low voltage, 5V tolerant buffer according to claim 13, further comprising:

providing a power supply voltage of no greater than 2.0V nominal.

16. The method of providing a low voltage, 5V tolerant buffer according to claim 13, further comprising:

providing a power supply voltage of no greater than 1.8V nominal.

17. The method of providing a low voltage, 5V tolerant buffer according to claim 13, wherein:

said buffer is comprised in a SCSI bus.

18. Apparatus for providing a low voltage, 5V tolerant buffer, comprising:

means for inverting an input signal to a series connection of an upper transistor, a central transistor, and a lower transistor;

means for connecting a terminal of said upper transistor to a PAD;

means for connecting a terminal of said lower transistor to ground;

means for providing a bias voltage to a gate of said upper transistor, said bias voltage being based on a difference between a power supply voltage and a voltage at said PAD; and

means for coupling a power supply input to a gate of said central transistor; and

means for providing an input stage adapted to be driven by a node between a central transistor and said lower transistor;

wherein said buffer is a bi-directional buffer.

19. The apparatus for providing a low voltage, 5V tolerant buffer according to claim 18, further comprising:

means for providing said power supply voltage of no greater than 2.5V nominal.

20. The apparatus for providing a low voltage, 5V tolerant buffer according to claim 18, further comprising:

means for coupling said power supply voltage of no greater than 2.0V nominal.

21. The apparatus for providing a low voltage, 5V tolerant buffer according to claim 18, further comprising:

means for providing said power supply voltage of no greater than 1.8V nominal.

22. The apparatus for providing a low voltage, 5V tolerant buffer according to claim 18, wherein:

said buffer is comprised in a SCSI bus.

23. A low voltage, 5V tolerant buffer, comprising:

a series connection of at least three transistors, a terminal of an upper transistor in said series connection being connected to a PAD, and a terminal of a lower transistor of said series connection being connected to ground; and

a bias generator, an output of said bias generator being connected to a gate of said upper transistor;

wherein a gate of a central one of said series connection of three transistors is adapted to be connected to a power supply of no greater than 2.5V nominal; and

wherein said bias generator comprises a series connection of two transistors between said power supply and said PAD.

24. The low voltage, 5V tolerant buffer according to claim 23, wherein:

an upper transistor of said bias generator has a gate being connected to said PAD.

25. The low voltage, 5V tolerant buffer according to claim 24, wherein:

a lower transistor of said bias generator has a gate being connected to said power supply.

26. A low voltage, 5V tolerant buffer, comprising:

a series connection of at least three transistors, a terminal of an upper transistor in said series connection being connected to a PAD, and a terminal of a lower transistor of said series connection being connected to ground; and

a bias generator, an output of said bias generator being connected to a gate of said upper transistor, said bias generator comprising;

a series connection of two p-channel field effect transistors, a gate of one of said two transistors is adapted to be coupled to said PAD, and a gate of the other of said two transistors is adapted to be driven by said power supply, and

said series connection of said two transistors being connected between said power supply and said PAD;

wherein a gate of a central one of said series connection of three transistors is adapted to be connected to a power supply of no greater than 2.5V nominal.