Moderate current 5V tolerant buffer using a 2.5 volt power supply
First Claim
1. A low voltage, 5V tolerant buffer, comprising:
- a series connection of at least three transistors, a terminal of an upper transistor in said series connection being connected to a PAD, and a terminal of a lower transistor of said series connection being connected to ground;
a bias generator, an output of said bias generator being connected to a gate of said upper transistor; and
an input stage driven by a node between said central transistor and said lower transistor;
wherein a gate of a central one of said series connection of three transistors is adapted to be connected to a power supply of no greater than 2.5V nominal; and
said buffer is a bi-directional buffer.
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Accused Products
Abstract
A low voltage, 5V tolerant open drain output buffer having moderate current tolerance capabilities is formed with 3.3V technology using a nominal power supply of 2.5V or less. The buffer includes an inverter, a series connection of the current paths of three n-channel FET transistors, and a backgate bias generator. One terminal of the series connection of three transistors is connected to a PAD, and the other terminal of the lower transistor of the series is connected to ground. The bias generator is formed using two p-channel field effect transistors (FETs) that are cross-connected between VDD and the PAD. A gate of a central one of the three transistors is connected to the power supply. An output of the bias generator is connected to a gate of the upper transistor. The inventive buffer may be manufactured using standard 3.3V processes, but functions with a power supply of, e.g., 2.5V or 1.8V.
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Citations
26 Claims
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1. A low voltage, 5V tolerant buffer, comprising:
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a series connection of at least three transistors, a terminal of an upper transistor in said series connection being connected to a PAD, and a terminal of a lower transistor of said series connection being connected to ground; a bias generator, an output of said bias generator being connected to a gate of said upper transistor; and an input stage driven by a node between said central transistor and said lower transistor; wherein a gate of a central one of said series connection of three transistors is adapted to be connected to a power supply of no greater than 2.5V nominal; and said buffer is a bi-directional buffer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of providing a low voltage, 5V tolerant buffer, comprising:
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providing a series connection of at least three transistors; connecting an end of an upper transistor in said series connection to a PAD; connecting an end of a lower transistor of said series connection to ground; providing a bias voltage to a gate of said upper transistor, said bias voltage being based on a difference between a power supply voltage and a voltage at said PAD; providing a power supply input to a gate of a central one of said series connection of three transistors; and providing an input stage adapted to be driven by a node between said central transistor and said lower transistor. - View Dependent Claims (14, 15, 16, 17)
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18. Apparatus for providing a low voltage, 5V tolerant buffer, comprising:
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means for inverting an input signal to a series connection of an upper transistor, a central transistor, and a lower transistor; means for connecting a terminal of said upper transistor to a PAD; means for connecting a terminal of said lower transistor to ground; means for providing a bias voltage to a gate of said upper transistor, said bias voltage being based on a difference between a power supply voltage and a voltage at said PAD; and means for coupling a power supply input to a gate of said central transistor; and means for providing an input stage adapted to be driven by a node between a central transistor and said lower transistor; wherein said buffer is a bi-directional buffer. - View Dependent Claims (19, 20, 21, 22)
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23. A low voltage, 5V tolerant buffer, comprising:
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a series connection of at least three transistors, a terminal of an upper transistor in said series connection being connected to a PAD, and a terminal of a lower transistor of said series connection being connected to ground; and a bias generator, an output of said bias generator being connected to a gate of said upper transistor; wherein a gate of a central one of said series connection of three transistors is adapted to be connected to a power supply of no greater than 2.5V nominal; and wherein said bias generator comprises a series connection of two transistors between said power supply and said PAD. - View Dependent Claims (24, 25)
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26. A low voltage, 5V tolerant buffer, comprising:
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a series connection of at least three transistors, a terminal of an upper transistor in said series connection being connected to a PAD, and a terminal of a lower transistor of said series connection being connected to ground; and a bias generator, an output of said bias generator being connected to a gate of said upper transistor, said bias generator comprising; a series connection of two p-channel field effect transistors, a gate of one of said two transistors is adapted to be coupled to said PAD, and a gate of the other of said two transistors is adapted to be driven by said power supply, and said series connection of said two transistors being connected between said power supply and said PAD; wherein a gate of a central one of said series connection of three transistors is adapted to be connected to a power supply of no greater than 2.5V nominal.
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Specification