Frequency locked loop
First Claim
1. A microcontroller integrated circuit, comprising:
- a terminal;
a crystal oscillator circuit coupled to the terminal, the crystal oscillator circuit outputting a first clock signal of a first frequency;
a real time clock that receives the first clock signal;
a processor having a clock input lead; and
a clock multiplier circuit having an input lead and an output lead, the clock multiplier circuit receiving the first clock signal from the crystal oscillator circuit and generating therefrom a second clock signal, the second clock signal having a second frequency that is a multiple of the first frequency, wherein the second clock signal is supplied to the clock input lead of the processor, wherein the clock multiplier circuit includes a frequency locked loop, the frequency locked loop including a digital filter, wherein the frequency locked loop frequency locks a first signal with respect to a second signal, the frequency locked loop further including a ramp generator, wherein the ramp generator starts a first ramp upon a first edge of the first signal, and wherein a first digital value indicative of a magnitude of the first ramp is determined upon a first edge of the second signal, and wherein the ramp generator starts a second ramp upon a second edge of the first signal, and wherein a second digital value indicative of a magnitude of the second ramp is determined upon a second edge of the second signal, the first and second digital values being used to generate a third digital value, the third digital value being supplied to the digital filter.
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Accused Products
Abstract
A frequency locked loop in a microcontroller integrated circuit has a precision digital feedback control loop. The frequency locked loop performs a clock multiplication function such that an inexpensive and low frequency external crystal is usable to both clock a processor of the microcontroller with a higher frequency and low-jitter clock signal and to clock a real time clock of the microcontroller with a low frequency time base that is a power of two multiple of one hertz. In one embodiment, the digital feedback control loop includes a ramp generator, a digital filter, and a loop divider. The ramp generator is controlled to output steeper and steeper ramps as the frequency locking process proceeds toward frequency lock. A preset value that presets the loop divider is changed to adjust the phase of a feedback signal with respect to a reference input signal.
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Citations
13 Claims
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1. A microcontroller integrated circuit, comprising:
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a terminal; a crystal oscillator circuit coupled to the terminal, the crystal oscillator circuit outputting a first clock signal of a first frequency; a real time clock that receives the first clock signal; a processor having a clock input lead; and a clock multiplier circuit having an input lead and an output lead, the clock multiplier circuit receiving the first clock signal from the crystal oscillator circuit and generating therefrom a second clock signal, the second clock signal having a second frequency that is a multiple of the first frequency, wherein the second clock signal is supplied to the clock input lead of the processor, wherein the clock multiplier circuit includes a frequency locked loop, the frequency locked loop including a digital filter, wherein the frequency locked loop frequency locks a first signal with respect to a second signal, the frequency locked loop further including a ramp generator, wherein the ramp generator starts a first ramp upon a first edge of the first signal, and wherein a first digital value indicative of a magnitude of the first ramp is determined upon a first edge of the second signal, and wherein the ramp generator starts a second ramp upon a second edge of the first signal, and wherein a second digital value indicative of a magnitude of the second ramp is determined upon a second edge of the second signal, the first and second digital values being used to generate a third digital value, the third digital value being supplied to the digital filter. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A microcontroller integrated circuit, comprising:
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a terminal; a crystal oscillator circuit coupled to the terminal, the crystal oscillator circuit outputting a first clock signal of a first frequency; a real time clock that receives the first clock signal; a processor having a clock input lead; and a clock multiplier circuit having an input lead and an output lead, the clock multiplier circuit receiving the first clock signal from the crystal oscillator circuit and generating therefrom a second clock signal, the second clock signal having a second frequency that is a multiple of the first frequency, wherein the second clock signal is supplied to the clock input lead of the processor, wherein the clock multiplier circuit includes a control loop, the control loop including an oscillator and a loop divider, the loop divider being a counter that is preset with a preset value, and wherein a phase of the second signal is adjusted with respect to the first signal by changing the preset value. - View Dependent Claims (10, 11, 12, 13)
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Specification