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One-time programming multiple-level memory cells

  • US 7,002,832 B2
  • Filed: 10/27/2003
  • Issued: 02/21/2006
  • Est. Priority Date: 10/31/2002
  • Status: Active Grant
First Claim
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1. A multiple-level memory cell, comprising:

  • a storage element formed of several polysilicon resistors connected in series between two input/output terminals;

    a load in series with said resistive element, the junction point thereof forming a read terminal of the memory cell, and the respective junctions between said resistors of the storage element being accessible; and

    wherein at least certain points among said junctions of the storage element and the junction of this element with the load, are connectable, individually by a switch, either to one of said input/output terminals of the storage element, or to a terminal of application of a predetermined voltage, wherein individual programming of the resistors may be performed.

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