Semiconductor memory device which selectively controls a local input/output line sense amplifier

• US 7,002,858 B2
• Filed: 07/16/2004
• Issued: 02/21/2006
• Est. Priority Date: 07/24/2003
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Dong-Su
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, NAM THANH
• Application Number:
  US10/892,361
• Publication Number:
  US 20050018511A1
• Time in Patent Office: 585 Days
• Field of Search: 365/200, 365/207, 365/210
• US Class Current: 365/200
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 29/83 with reduced power consumption
• CPC Class Codes: G11C 29/832 with disconnection of faulty elements
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage

Abstract

A semiconductor memory device in which a local input/output line sense amplifier may be selectively enabled or disabled. The semiconductor memory device may include a memory cell array block, a redundancy circuit, a switch unit, and/or a control unit. The memory cell array block may include a local input/output line sense amplifier that operates in response to a sense amplifier enable signal. The redundancy circuit may include a redundancy local input/output line sense amplifier that operates in response to the sense amplifier enable signal. The switch unit may selectively output data output from the local input/output line sense amplifier or the redundancy local input/output line sense amplifier, in response to a first select signal and a second select signal. If the redundancy circuit operates, the control unit may generate, in response to the second select signal, a sense amplifier operation control signal that disables the local input/output line sense amplifier. Since the semiconductor memory device selectively enables or disables the local input/output line sense amplifier, unnecessary current consumption caused due to dummy sensing is avoided.

Claims

1. A semiconductor memory device which selectively controls a local input/output line sense amplifier, wherein the semiconductor memory device comprises:

a memory cell array block, which includes a local input/output line sense amplifier which operates in response to a sense amplifier enable signal;

a redundancy circuit, which includes a redundancy local input/output line sense amplifier which operates in response to the sense amplifier enable signal;

a switch unit, which selectively outputs data output from the local input/output line sense amplifier or the redundancy local input/output line sense amplifier in response to a first select signal and a second select signal; and

a control unit which generates in response to the second select signal a sense amplifier operation control signal that disables the local input/output line sense amplifier, if the redundancy circuit operates.

2. The semiconductor memory device of claim 1, wherein the control unit generates, in response to the second select signal, a redundancy sense amplifier operation control signal that disables the redundancy local input/output line sense amplifier, if the redundancy circuit does not operate.

3. The semiconductor memory device of claim 2, wherein the redundancy local input/output line sense amplifier comprises:

a first redundancy transistor, which has a first interface connected to a redundancy inverted global input/output line and a gate to which the sense amplifier enable signal is applied;

a second redundancy transistor, which has a first interface connected to a redundancy global input/output line and a gate to which the sense amplifier enable signal is applied;

a third redundancy transistor, which has a first interface connected to a second interface of the first redundancy transistor and a gate to which the data output from a redundancy local input/output line is applied;

a fourth redundancy transistor, which has a first interface connected to a second interface of the second redundancy transistor and a gate to which inverted data output from a redundancy inverted local input/output line is applied;

a fifth redundancy transistor, which has a first interface connected to both the second interface of the third redundancy transistor and the second interface of the fourth redundancy transistor, and a gate to which the sense amplifier enable signal is applied; and

a redundancy control transistor, which has a first interface connected to a second interface of the fifth redundancy transistor, a gate to which the redundancy sense amplifier operation control signal is applied, and a second interface is connected to a ground voltage.

4. The semiconductor memory device of claim 2, wherein the redundancy sense amplifier operation control signal has the same logic level as that of the second select signal.

5. The semiconductor memory device of claim 2, wherein the redundancy sense amplifier operation control signal is applied to the redundancy local input/output line sense amplifier via a transmission line located on the redundancy circuit.

6. The semiconductor memory device of claim 1, wherein the first select signal has the opposite logic level as the second select signal, the second select signal is a column redundancy enable signal, and the sense amplifier operation control signal has the opposite logic level as the second select signal.

7. The semiconductor memory device of claim 1, wherein the switch unit comprises:

a first output unit, which outputs or cuts off the data output from the local input/output sense amplifier in response to the first select signal; and

a second output unit, which outputs or cuts off the data output from the redundancy local input/output sense amplifier in response to the second select signal.

8. The semiconductor memory device of claim 1, wherein the local input/output line sense amplifier comprises:

a first transistor, which has a first interface connected to an inverted global input/output line and a gate to which the sense amplifier enable signal is applied;

a second transistor, which has a first interface connected to a global input/output line and a gate to which the sense amplifier enable signal is applied;

a third transistor, which has a first interface connected to a second end of the first transistor and a gate to which the data output from a local input/output line is applied;

a fourth transistor, which has a first interface connected to a second interface of the second transistor and a gate to which inverted data output from an inverted local input/output line is applied;

a fifth transistor, which has a first interface connected to both the second interface of the third transistor and the second interface of the fourth transistor, and a gate to which the sense amplifier enable signal is applied; and

a control transistor, which has a first interface connected to a second interface of the fifth transistor, a gate to which the sense amplifier operation control signal is applied, and a second interface connected to a ground voltage.

9. The semiconductor memory device of claim 1, wherein the sense amplifier operation control signal is applied to the local input/output line sense amplifier via a transmission line located on the memory cell array block.

10. A semiconductor memory device which selectively controls a local input/output line sense amplifier, wherein the semiconductor memory device comprises:

an upper memory cell array block, which includes an upper local input/output line sense amplifier which operates in response to an upper sense amplifier enable signal;

an upper redundancy circuit, which includes an upper redundancy local input/output line sense amplifier which operates in response to the upper sense amplifier enable signal;

a lower memory cell array block, which includes a lower local input/output line sense amplifier which operates in response to a lower sense amplifier enable signal;

a lower redundancy circuit, which includes a lower redundancy local input/output line sense amplifier that operates in response to the lower sense amplifier enable signal;

a switch unit, which selectively outputs data output from the upper local input/output line sense amplifier, the upper redundancy local input/output line sense amplifier, or the lower redundancy local input/output line sense amplifier in response to a first select signal, a second upper select signal, and a second lower select signal; and

a control unit which;

generates, in response to the second upper select signal, an upper sense amplifier operation control signal which disables the upper local input/output line sense amplifier, if the upper redundancy circuit operates; and

generates, in response to the second lower select signal, a lower sense amplifier operation control signal which disables the lower local input/output line sense amplifier, if the lower redundancy circuit operate.

11. The semiconductor memory device of claim 10, wherein:

the control unit generates, in response to the second upper select signal, an upper redundancy sense amplifier operation control signal which disables the upper redundancy local input/output line sense amplifier, if the upper memory cell array block operates; and

the control unit generates, in response to the second lower select signal, a lower redundancy sense amplifier operation control signal which disables the lower redundancy local input/output line sense amplifier, if the lower memory cell array block operates.

12. The semiconductor memory device of claim 11, wherein the upper redundancy sense amplifier operation control signal has the same logic level as the second upper select signal, and the lower redundancy sense amplifier operation control signal has the same logic level as the second lower select signal.

13. The semiconductor memory device of claim 11, wherein:

the upper redundancy sense amplifier operation control signal is applied to the upper redundancy local input/output line sense amplifier via a transmission line located on the upper redundancy circuit; and

the lower redundancy sense amplifier operation control signal is applied to the lower redundancy local input/output line sense amplifier via a transmission line located on the lower redundancy circuit.

14. The semiconductor memory device of claim 10, wherein if one of the first select signal, the second upper select signal, and the second lower select signal is at a first level, the other two signals are at a second level.

15. The semiconductor memory device of claim 10, wherein:

the upper sense amplifier operation control signal has the opposite logic level to that of the second upper select signal; and

the lower sense amplifier operation control signal has the opposite logic level to that of the second lower select signal.

16. The semiconductor memory device of claim 10, wherein the switch unit comprises:

a first output unit, which outputs or cuts off the data output from the upper local input/output sense amplifier in response to the first select signal;

a second upper output unit, which outputs or cuts off the data output from the upper redundancy local input/output sense amplifier in response to the second upper select signal; and

a second lower output unit, which outputs or cuts off the data output from the lower redundancy local input/output sense amplifier in response to the second lower select signal.

17. The semiconductor memory device of claim 10, wherein:

the upper sense amplifier operation control signal is applied to the upper local input/output line sense amplifier via a transmission line located on the upper memory cell array block; and

the lower sense amplifier operation control signal is applied to the lower local input/output line sense amplifier via a transmission line located on the lower memory cell array block.

18. A semiconductor memory device which selectively controls a local input/output line sense amplifier, the semiconductor memory device comprising:

an upper memory cell array block, which includes an upper local input/output line sense amplifier that operates in response to an upper sense amplifier enable signal;

a redundancy circuit, which includes an upper redundancy local input/output line sense amplifier that operates in response to the upper sense amplifier enable signal;

a lower memory cell array block, which outputs stored data to an input/output line;

a lower redundancy circuit, which includes a lower redundancy local input/output line sense amplifier that operates in response to the lower sense amplifier enable signal;

a switch unit, which selectively outputs data output from the upper local input/output line sense amplifier, the upper redundancy local input/output line sense amplifier, or the lower redundancy local input/output line sense amplifier in response to a first select signal, a second upper select signal, and a second lower select signal; and

a local input/output line directly connected to the input/output line.

19. The semiconductor memory device of claim 18, wherein the switch unit comprises:

a first output unit, which outputs or cuts off, in response to the first select signal, the data output from the upper local input/output sense amplifier to or from the input/output line;

a second output unit, which outputs or cuts off, in response to the second upper select signal, the data output from the upper redundancy local input/output sense amplifier to or from the input/output line; and

a second lower output unit, which outputs or cuts off, in response to the second lower select signal, the data output from the lower redundancy local input/output sense amplifier to or from the input/output line.

20. The semiconductor memory device of claim 18, further comprising a control unit, which generates, in response to the second upper select signal, an upper sense amplifier operation control signal that disables the upper local input/output line sense amplifier, if the upper redundancy circuit operates.

21. The semiconductor memory device of claim 20, wherein:

if one of the first select signal, the second upper select signal, and the second lower select signal is at a first level, the other two signals are at a second level; and

the upper sense amplifier operation control signal has the opposite logic level as the second upper select signal.

22. The semiconductor memory device of claim 20, wherein the upper sense amplifier operation control signal is applied to the upper local input/output line sense amplifier via a transmission line located on the upper memory cell array block.

23. The semiconductor memory device of claim 20, wherein:

if the upper memory cell array block operates, the control unit generates, in response to the second upper select signal, an upper redundancy sense amplifier operation control signal which disables the upper redundancy local input/output line sense amplifier; and

if the lower memory cell array block operates, the control unit generates, in response to the second lower select signal, a lower redundancy sense amplifier operation control signal which disables the lower redundancy local input/output line sense amplifier.

24. The semiconductor memory device of claim 23, wherein:

the upper redundancy sense amplifier operation control signal has the same logic level as the second upper select signal; and

the lower redundancy sense amplifier operation control signal has the same logic level as the second lower select signal.

25. The semiconductor memory device of claim 23, wherein:

the upper redundancy sense amplifier operation control signal is applied to the upper redundancy local input/output line sense amplifier via a transmission line located on the upper redundancy circuit; and

the lower redundancy sense amplifier operation control signal is applied to the lower redundancy local input/output line sense amplifier via a transmission line located on the lower redundancy circuit.