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VDD over and undervoltage measurement techniques using monitor cells

  • US 7,003,421 B1
  • Filed: 11/03/2003
  • Issued: 02/21/2006
  • Est. Priority Date: 11/03/2003
  • Status: Expired due to Term
First Claim
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1. A method for testing an integrated circuit chip comprising:

  • a) applying a first reference voltage to a first input of a first monitor cell of at least one monitor cell integrated on the chip, wherein each of the monitor cells comprises a comparator and a latch coupled to the output of the comparator;

    b) applying a first test voltage from a selected portion of the chip to a second input of the first monitor cell;

    c) comparing the first reference voltage to the first test voltage using the comparator for providing a first result for storage in the latch of the first monitor cell;

    d) applying a second reference voltage having a value different from the first reference voltage to the first input of the first monitor cell;

    e) comparing the second reference voltage to the first test voltage using the comparator for providing a second result in the latch of the first monitor cell; and

    f) analyzing the first and second results to determine a value for the first test voltage.

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