VDD over and undervoltage measurement techniques using monitor cells

• US 7,003,421 B1
• Filed: 11/03/2003
• Issued: 02/21/2006
• Est. Priority Date: 11/03/2003
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Castaneda, David, Allen, Ernest III
• Primary Examiner(s): NGHIEM, MICHAEL P
• Application Number:
  US10/700,790
• Time in Patent Office: 841 Days
• Field of Search: 702/57, 702/60, 702 63- 65, 702/107, 702117-121, 327/3, 327/7, 327/56, 327/57, 324/73.1, 324/76.11, 324/76.39, 324/763, 324/765
• US Class Current: 702/117
• CPC Class Codes: G01R 19/16552 in I.C. power supplies

Abstract

According to one embodiment, a method of testing an integrated circuit is provided. A reference voltage is coupled to each of a first and second comparator integrated on the chip. A supply voltage is compared to the reference voltage in a comparator to determine overvoltage or undervoltage conditions. The results of the comparison are stored and sizing and placing of at least one decoupling circuit in the circuit design is made based on the stored determinations.

Claims

1. A method for testing an integrated circuit chip comprising:

a) applying a first reference voltage to a first input of a first monitor cell of at least one monitor cell integrated on the chip, wherein each of the monitor cells comprises a comparator and a latch coupled to the output of the comparator;

b) applying a first test voltage from a selected portion of the chip to a second input of the first monitor cell;

c) comparing the first reference voltage to the first test voltage using the comparator for providing a first result for storage in the latch of the first monitor cell;

d) applying a second reference voltage having a value different from the first reference voltage to the first input of the first monitor cell;

e) comparing the second reference voltage to the first test voltage using the comparator for providing a second result in the latch of the first monitor cell; and

f) analyzing the first and second results to determine a value for the first test voltage.

2. The method as recited in claim 1 further comprising adding a decoupling circuit to a selected portion of the chip based on the first and second results and repeating steps a) through f) after adding the decoupling circuit.

3. The method as recited in claim 1 further comprising applying sequentially the first reference voltage and the second reference voltage to a first input of a second of the at least one monitor cells and applying a second test voltage from a second selected portion of the chip to a second input of the second monitor cell.

4. The method as recited in claim 3 further comprising:

comparing the first reference voltage to the second test voltage using the comparator for providing a first result for storage in the latch of the second monitor cell;

comparing the second reference voltage to the second test voltage using the comparator for providing a second result in the latch of the second monitor cell; and

analyzing the first ands second results of the second monitor cell to determine a value for the second test voltage.

5. The method as recited in claim 4 further comprising analyzing the values determined for the first and second test voltages to determine a size and location for decoupling circuitry to be coupled to the chip.

6. The method as recited in claim 3 wherein the first and second test voltages are power supply voltages taken at different locations on the chip.

7. The method as recited in claim 1 wherein the second reference voltage is obtained by adjusting the first reference voltage to a new level.

8. The method as recited in claim 1 wherein testing is performed using automated test equipment and the first and second reference voltages are supplied by the ATE.

9. The method as recited in claim 1 wherein the testing is performed during the application of a scan chain to the chip.

10. The method as recited in claim 5 wherein the chip is a prototype chip and the decoupling circuitry is added to the design of the chip.

11. The method as recited in claim 1 wherein comparing the first reference voltage to the first test voltage and comparing the second reference voltage to the first test voltage comparison making a determination as to at least one of whether the first test voltage is less than the reference voltage when testing for undervoltage conditions or whether the first test voltage exceeds the reference voltage when testing for overvoltage conditions.

12. The method as recited in claim 1 wherein the comparing comprises making a determination as to whether the first reference voltage and the second reference voltage exceeds the first test voltage when testing for overvoltage conditions.

13. The method as recited in claim 1 wherein the comparing comprises making a determination as to whether the first reference voltage or the second reference voltage is less than the first test voltage when testing for undervoltage conditions.

14. A method of testing an integrated circuit comprising:

a) providing an overvoltage reference voltage and supply voltage to a first voltage comparator;

b) providing an undervoltage reference voltage and the supply voltage to a second digital comparator;

c) making a first determination for the first voltage comparator whether the overvoltage reference voltage exceeds the supply voltage;

d) making a second determination for the second comparator whether the supply voltage exceeds the undervoltage reference voltage; and

e) storing the first and second determinations in a first and a second latch attached respectively to the first and second comparators.

15. The method as recited in claim 14 further comprising adjusting the overvoltage reference voltage and the undervoltage reference voltage and repeating steps c) through e) and determining the value for the supply voltage from the stored results.

16. The method as recited in claim 15 further comprising duplicating each of the steps recited for claim 15 for a plurality of locations across the integrated circuit, each of the locations potentially having a different supply voltage than other of the locations.

17. The method as recited in claim 16 further comprising analyzing the values determined for the supply voltage to determine a size and location for adding decoupling circuitry.

18. An integrated circuit adapted for voltage level detection, the integrated circuit comprising:

a plurality of voltage supply conductors configured for providing a power supply voltage to the integrated circuit; and

a monitor cell integrated in the integrated circuit for testing over and under voltage conditions, the monitor cell comprising a first digital voltage comparator and a second digital voltage comparator each of the comparators coupled respectively to an associated latch for receiving the output of the voltage comparator, wherein;

inputs to the first comparator comprise a supply voltage from one of the plurality of supply conductors and an overvoltage reference voltage;

inputs to the second comparator comprise the supply voltage from the one of the plurality of supply conductors and an undervoltage reference voltage; and

wherein the monitor cell is further configured to receive at an input of the first comparator and at an input of the second comparator a reference voltage provided by one of the plurality of voltage supply conductors for comparison with the supply voltage.

19. An integrated circuit adapted for voltage level detection, the integrated circuit comprising:

a plurality of voltage supply conductors configured for providing a power supply voltage to the integrated circuit; and

a monitor cell integrated in the integrated circuit for testing over and under voltage conditions, the monitor cell comprising a first digital voltage comparator and a second digital voltage comparator each of the comparators coupled respectively to an associated latch for receiving the output of the voltage comparator, wherein;

inputs to the first comparator comprise a supply voltage from one of the plurality of supply conductors and an overvoltage reference voltage;

inputs to the second comparator comprise the supply voltage from the one of the plurality of supply conductors and an undervoltage reference voltage; and

wherein the monitor cell is configured to receive a reference voltage from automated test equipment and to transmit outputs of the associated latches to the automated test equipment.

20. An integrated circuit adapted for voltage level detection, the integrated circuit comprising:

a plurality of voltage supply conductors configured for providing a power supply voltage to the integrated circuit; and

a monitor cell integrated in the integrated circuit for testing over and under voltage conditions, the monitor cell comprising a first digital voltage comparator and a second digital voltage comparator each of the comparators coupled respectively to an associated latch for receiving the output of the voltage comparator, wherein the latches of monitor cell each include a timer configured to timestamp occurrences of overvoltage incidents and undervoltage incidents and wherein;

inputs to the first comparator comprise a supply voltage from one of the plurality of supply conductors and an overvoltage reference voltage; and

inputs to the second comparator comprise the supply voltage from the one of the plurality of supply conductors and an undervoltage reference voltage.