Method of manufacturing a thin film transistor array

• US 7,005,331 B2
• Filed: 06/29/2004
• Issued: 02/28/2006
• Est. Priority Date: 12/03/2003
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: Quanta Display Incorporated (AUO Corp.)
• Inventors: Chen, Hung-De
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Malsawma, Lex H.
• Application Number:
  US10/878,320
• Publication Number:
  US 20050124088A1
• Time in Patent Office: 609 Days
• Field of Search: 438/30, 438/151, 438/158
• US Class Current: 438/158
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate

Abstract

A method for manufacturing a thin film transistor array substrate is disclosed. A first metal layer, a gate insulating layer, a semiconductor layer, an ohmic contact layer and a second metal layer are sequentially formed over a substrate, and a first patterning process is carried out to define a source/drain electrodes area, a scan line area, a data line area, a terminal contact area and a pixel area. An interlayer insulating layer is formed, and a second patterning process is implemented to form a source/drain contact hole, a scan line contact hole and a terminal contact hole. A transparent conductive layer, a third metal layer and a passivation layer are sequentially formed over the substrate to achieve electrical contacts among above-mentioned contact holes, and a third patterning process is then implemented to form a thin film transistor, a scan line, a data line, a terminal contact and a pixel electrode.

Claims

1. A method for manufacturing a thin film transistor array substrate, comprising the steps of:

providing a substrate;

forming a first metal layer, a gate insulating layer, a semiconductor layer, an ohmic contact layer and a second metal layer over the substrate, and then carrying out a first patterning process to define a source/drain electrodes area, a scan line area, a data line area, a terminal contact area and a pixel area;

forming an interlayer insulating layer over the substrate, and carrying out a second patterning process to define a source/drain contact hole, a data line contact hole and a terminal contact hole; and

forming a transparent conductive layer, a third metal layer and a passivation layer to protect over the substrate and achieve electrical connections among the source/drain contact hole, the data line contact hole and the terminal contact hole, and then carrying out a third patterning process to form a thin film transistor, a scan line, a data line, a terminal contact and a pixel electrode.

2. The method as claimed in claim 1, wherein the first patterning process including:

forming on part of the second metal layer a first photoresist layer having a first area and a second area, of which the thickness is thinner than the thickness of the first area;

etching the second metal layer, the ohmic contact layer, the semiconductor layer, the gate insulating layer and the first metal layer which are not covered by the first photoresist layer to define a predetermined TFT area, the scan line area, the data line area and the pixel area; and

removing the second area of the first photoresist layer to expose the second metal layer, and then etching the exposed second metal layer and the ohmic contact layer thereunder to define the source/drain electrodes area and the terminal contact area.

3. The method as claimed in claim 2, wherein the second area of the first photoresist layer is removed by ashing.

4. The method as claimed in claim 2, wherein the first photoresist layer is formed by using a mask having a substantially transparent area, a partially transparent area and a substantially opaque area, the substantially opaque area is corresponding to the first area, and the partially transparent area is corresponding to the second area.

5. The method as claimed in claim 1, wherein the second patterning process including:

forming on part of the interlayer insulating layer a second photoresist layer having a third area and a fourth area, of which the thickness is thinner than the thickness of the third area;

etching the interlayer insulating layer and the semiconductor layer which are not covered by the second photoresist layer to define a predetermined terminal contact hole area; and

removing the fourth area of the second photoresist layer to expose the interlayer insulating layer, and then etching the exposed interlayer insulating layer, the semiconductor layer thereunder and the gate insulating layer in the predetermined terminal contact hole area to form the source/drain contact hole, the data line contact hole and the terminal contact hole.

6. The method as claimed in claim 1, wherein the second patterning process including:

forming on part of the interlayer insulating layer a second photoresist layer having a third area and a fourth area, of which the thickness is thinner than the thickness of the third area;

etching the interlayer insulating layer that is not covered by the second photoresist layer to define a predetermined terminal contact hole area; and

removing the fourth area of the second photoresist layer to expose the interlayer insulating layer, and then etching the exposed interlayer insulating layer, and the gate insulating layer and the semiconductor layer in the predetermined terminal contact hole area to form the source/drain contact hole, the data line contact hole and the terminal contact hole.

7. The method as claimed in claim 1, wherein the third patterning process including:

forming on part of the passivation layer a third photoresist layer having a fifth area and a sixth area, of which the thickness is thinner than the thickness that of the fifth area;

etching the passivation layer and the third metal layer which are not covered by the third photoresist layer to expose the transparent conductive layer and thereby to define a predetermined source/drain disconnection area;

removing the sixth area of the third photoresist layer to expose the passivation layer, and then etching the exposed passivation layer;

etching the transparent conductive layer that is exposed, in particular the transparent conductive layer in the predetermined source/drain disconnection area, to terminate the electrical connection between the source electrode and the drain electrode as well as the electrical connection between the TFT area and the scan line area; and

etching the third metal layer that is exposed to expose the transparent conductive layer in the terminal contact area and in the pixel area, and thereby to form the thin film transistor, the scan line, the data line, the terminal contact and the pixel electrode.

8. A method for manufacturing a thin film transistor array substrate, comprising the steps of:

providing a substrate;

forming a first metal layer, a gate insulating layer, a semiconductor layer, an ohmic contact layer and a second metal layer over the substrate, and then carrying out a first patterning process to define a source/drain electrodes area, a scan line area, a data line area, a terminal contact area and a pixel area;

forming an interlayer insulating layer over the substrate, and carrying out a second patterning process to form a source/drain contact hole, a scan line contact hole and a terminal contact hole; and

forming a transparent conductive layer, a third metal layer and a passivation layer to protect over the substrate and achieve electrical connections among the source/drain contact hole, the scan line contact hole and the terminal contact hole, and then carrying out a third patterning process to form a thin film transistor, a scan line, a data line, a terminal contact and a pixel electrode.

9. The method as claimed in claim 8, wherein the first patterning process including:

forming on part of the second metal layer a first photoresist layer having a first area and a second area, of which the thickness is thinner than the thickness of the first area;

etching the second metal layer, the ohmic contact layer, the semiconductor layer, the gate insulating layer and the first metal layer which are not covered by the first photoresist layer to define a predetermined TFT area, the scan line area, the data line area and the pixel area; and

removing the second area of the first photoresist layer to expose the second metal layer, and then etching the exposed second metal layer and the ohmic contact layer thereunder to define the source/drain electrodes area and the terminal contact area.

10. The method as claimed in claim 9, wherein the second area of the first photoresist layer is removed by ashing.

11. The method as claimed in claim 9, wherein the first photoresist layer is formed by using a mask having a substantially transparent area, a partially transparent area and a substantially opaque area, the substantially opaque area is corresponding to the first area, and the partially transparent area is corresponding to the second area.

12. The method as claimed in claim 8, wherein the second patterning process including:

forming on part of the interlayer insulating layer a second photoresist layer having a third area and a fourth area, of which the thickness is thinner than the thickness of the third area;

etching the interlayer insulating layer and the semiconductor layer which are not covered by the second photoresist layer to define a predetermined terminal contact hole area; and

removing the fourth area of the second photoresist layer to expose the interlayer insulating layer, and then etching the exposed interlayer insulating layer, the semiconductor layer thereunder and the gate insulating layer in the predetermined terminal contact hole area to form the source/drain contact hole, the scan line contact hole and the terminal contact hole.

13. The method as claimed in claim 8, wherein the second patterning process including:

forming on part of the interlayer insulating layer a second photoresist layer having a third area and a fourth area, of which the thickness is thinner than the thickness of the third area;

etching the interlayer insulating layer that is not covered by the second photoresist layer to define a predetermined terminal contact hole area; and

removing the fourth area of the second photoresist layer to expose the interlayer insulating layer, and then etching the exposed interlayer insulating layer, the semiconductor layer thereunder and the semiconductor layer and the gate insulating layer in the predetermined terminal contact hole area to form the source/drain contact hole, the scan line contact hole and the terminal contact hole.

14. The method as claimed in claim 8, wherein the third patterning process including:

forming on part of the passivation layer a third photoresist layer having a fifth area and a sixth area, of which the thickness is thinner than that of the fifth area;

etching the passivation layer and the third metal layer which are not covered by the third photoresist layer to expose the transparent conductive layer and thereby to define a predetermined source/drain disconnection area;

removing the sixth area of the third photoresist layer to expose the passivation layer, and then etching the exposed passivation layer;

etching the transparent conductive layer that is exposed, in particular the transparent conductive layer in the predetermined source/drain disconnection area, to terminate the electrical connection between the source electrode and the drain electrode as well as the electrical connection between the TFT area and the scan line area; and

etching the third metal layer that is exposed to expose the transparent conductive layer in the terminal contact area and in the pixel area, and thereby to form the thin film transistor, the scan line, the data line, the terminal contact and the pixel electrode.

15. A method for manufacturing a thin film transistor array substrate, comprising the steps of:

providing a substrate;

forming a first metal layer, a gate insulating layer, a semiconductor layer, an ohmic contact layer and a second metal layer over the substrate, and then carrying out a first patterning process to define a source/drain electrodes area, a scan line area, a data line area, a terminal contact area and a pixel area;

forming an interlayer insulating layer over the substrate, and carrying out a second patterning process to form a source/drain contact hole, a data line contact hole and a terminal contact hole; and

forming a third metal layer and a passivation layer to protect over the substrate and achieve electrical connections among the source/drain contact hole, the data line contact hole and the terminal contact hole, and then carrying out a third patterning process to form a thin film transistor, a scan line, a data line, a terminal contact and a reflective pixel electrode.

16. The method as claimed in claims 15, wherein the third patterning process including:

forming on part of the passivation layer a third photoresist layer having a fifth area and a sixth area, of which the thickness is thinner than the thickness of the fifth area;

etching the passivation layer and the third metal layer which are not covered by the third photoresist layer to terminate the electrical connection between the source electrode and the drain electrode as well as the electrical connection between the TFT area and the scan line area; and

removing the sixth area of the third photoresist layer to expose the passivation layer, then etching the exposed passivation layer to expose the third metal layer in the pixel area, and thereby forming the thin film transistor, the scan line, the data line, the terminal contact and the reflective pixel electrode.

17. The method as claimed in claim 16, wherein the sixth area of the third photoresist layer is removed by ashing.

18. The methods as claimed in claim 16, wherein the third photoresist layer is formed by using a mask having a substantially transparent area, a partially transparent area and a substantially opaque area, the substantially opaque area is corresponding to the fifth area, and the partially transparent area is corresponding to the sixth area.

19. A method for manufacturing a TFT array substrate, comprising the steps of:

providing a substrate;

forming a first metal layer, a gate insulating layer, a semiconductor layer, an ohmic contact layer and a second metal layer over the substrate, and then carrying out a first patterning process to define a source/drain electrodes area, a scan line area, a data line area, a terminal contact area and a pixel area;

forming an interlayer insulating layer over the substrate, and carrying out a second patterning process to form a source/drain contact hole, a scan line contact hole and a terminal contact hole; and

forming at third metal layer and a passivation layer to protect over the substrate and achieve electrical connections among the source/drain contact hole, the scan line contact hole and the terminal contact hole, and then carrying out a third patterning process to form a thin film transistor, a scan line, a data line, a terminal contact and a reflective pixel electrode.

20. The method as claimed in claims 19, wherein the third patterning process including:

forming on part of the passivation layer a third photoresist layer having a fifth area and a sixth area, of which the thickness is thinner than the thickness of the fifth area;

etching the passivation layer and the third metal layer which are not covered by the third photoresist layer to terminate the electrical connection between the source electrode and the drain electrode as well as the electrical connection between the TFT area and the scan line area; and

removing the sixth area of the third photoresist layer to expose the passivation layer, then etching the exposed passivation layer to expose the third metal layer in the pixel area, and thereby forming the thin film transistor, the scan line, the data line, the terminal contact and the reflective pixel electrode.