Nonvolatile memory cell with a floating gate at least partially located in a trench in a semiconductor substrate
First Claim
1. A method for fabricating an integrated circuit comprising a first nonvolatile memory cell, the method comprising:
- forming a first trench in a top surface of a semiconductor substrate;
forming a dielectric on a surface of the first trench;
forming a conductive floating gate at least partially located in the first trench;
wherein the first nonvolatile memory cell comprises a first field effect transistor (FET) whose conductivity is at least partially controlled by the floating gate, and comprises a second FET for controlling access to the first FET;
wherein the method further comprises forming in the substrate;
a first semiconductor region of a first conductivity type adjacent to the first trench and providing a first source/drain region for the first FET;
a second semiconductor region of a second conductivity type adjacent to the first trench above the first semiconductor region and providing a channel region for the first FET;
a third semiconductor region of the first conductivity type, wherein at least a portion of the third semiconductor region lies adjacent to the first trench above the second semiconductor region and provides a second source/drain region for the first FET, wherein the third semiconductor region also provides a source/drain region for the second FET;
a fourth semiconductor region of the second conductivity type adjacent to the third semiconductor region and providing a channel region for the second FET; and
a fifth semiconductor region of the first conductivity type adjacent to the fourth semiconductor region and providing a source/drain region for the second FET; and
wherein the method further comprises forming a conductive member having a portion overlying the first trench, wherein the conductive member provides a gate for the second FET;
wherein the first and second source/drain regions of the first FET and the channel region of the first FET curve around the first trench.
2 Assignments
0 Petitions
Accused Products
Abstract
A floating gate (110) of a nonvolatile memory cell is formed in a trench (114) in a semiconductor substrate (220). A dielectric (128) covers the surface of the trench. The wordline (140) has a portion overlying the trench. The cell'"'"'s floating gate transistor has a first source/drain region (226), a channel region (224), and a second source/drain region (130). The dielectric (128) is stronger against leakage near at least a portion of the first source/drain region (122) than near at least a portion of the channel region. The stronger portion (128.1) of the additional dielectric improves data retention without increasing the programming and erase times if the programming and erase operations do not rely on a current through the stronger portion. Additional dielectric (210) has a portion located below the top surface of the substrate between the trench and a top part of the second source/drain region (130). The second source/drain region has a part located below the additional dielectric and meeting the trench. The additional dielectric can be formed with shallow trench isolation technology. The additional dielectric reduces the capacitance between the second source/drain region (130) and the floating gate.
58 Citations
39 Claims
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1. A method for fabricating an integrated circuit comprising a first nonvolatile memory cell, the method comprising:
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forming a first trench in a top surface of a semiconductor substrate; forming a dielectric on a surface of the first trench; forming a conductive floating gate at least partially located in the first trench; wherein the first nonvolatile memory cell comprises a first field effect transistor (FET) whose conductivity is at least partially controlled by the floating gate, and comprises a second FET for controlling access to the first FET; wherein the method further comprises forming in the substrate; a first semiconductor region of a first conductivity type adjacent to the first trench and providing a first source/drain region for the first FET; a second semiconductor region of a second conductivity type adjacent to the first trench above the first semiconductor region and providing a channel region for the first FET; a third semiconductor region of the first conductivity type, wherein at least a portion of the third semiconductor region lies adjacent to the first trench above the second semiconductor region and provides a second source/drain region for the first FET, wherein the third semiconductor region also provides a source/drain region for the second FET; a fourth semiconductor region of the second conductivity type adjacent to the third semiconductor region and providing a channel region for the second FET; and a fifth semiconductor region of the first conductivity type adjacent to the fourth semiconductor region and providing a source/drain region for the second FET; and wherein the method further comprises forming a conductive member having a portion overlying the first trench, wherein the conductive member provides a gate for the second FET; wherein the first and second source/drain regions of the first FET and the channel region of the first FET curve around the first trench. - View Dependent Claims (2, 3)
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4. A method for fabricating an integrated circuit comprising a first nonvolatile memory cell, the method comprising:
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forming a first trench in a top surface of a semiconductor substrate; forming a dielectric on a surface of the first trench; forming a conductive floating gate at least partially located in the first trench; wherein the first nonvolatile memory cell comprises a first field effect transistor (FET) whose conductivity is at least partially controlled by the floating gate, and comprises a second FET for controlling access to the first FET; wherein the method further comprises forming in the substrate; a first semiconductor region of a first conductivity type adjacent to the first trench and providing a first source/drain region for the first FET; a second semiconductor region of a second conductivity type adjacent to the first trench above the first semiconductor region and providing a channel region for the first FET; a third semiconductor region of the first conductivity type, wherein at least a portion of the third semiconductor region lies adjacent to the first trench above the second semiconductor region and provides a second source/drain region for the first FET, wherein the third semiconductor region also provides a source/drain region for the second FET; a fourth semiconductor region of the second conductivity type adjacent to the third semiconductor region and providing a channel region for the second FET; and a fifth semiconductor region of the first conductivity type adjacent to the fourth semiconductor region and providing a source/drain region for the second FET; and wherein the method further comprises forming a conductive member having a portion overlying the first trench, wherein the conductive member provides a gate for the second FET; wherein the method further comprises forming a dielectric region having at least a portion extending below the top surface of the substrate between the first trench and a top part of the third semiconductor region, wherein the third semiconductor region has a part located below said portion of the dielectric region and meeting the first trench. - View Dependent Claims (5, 6, 7, 8, 20, 21)
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9. A method for fabricating an integrated circuit comprising a first nonvolatile memory cell, the method comprising:
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forming a first trench in a top surface of a semiconductor substrate; forming a dielectric on a surface of the first trench; forming a conductive floating gate at least partially located in the first trench; wherein the first nonvolatile memory cell comprises a first field effect transistor (FET) whose conductivity is at least partially controlled by the floating gate, and comprises a second FET for controlling access to the first FET; wherein the method further comprises forming in the substrate; a first semiconductor region of a first conductivity type adjacent to the first trench and providing a first source/drain region for the first FET; a second semiconductor region of a second conductivity type adjacent to the first trench above the first semiconductor region and providing a channel region for the first FET; a third semiconductor region of the first conductivity type, wherein at least a portion of the third semiconductor region lies adjacent to the first trench above the second semiconductor region and provides a second source/drain region for the first FET, wherein the third semiconductor region also provides a source/drain region for the second FET; a fourth semiconductor region of the second conductivity type adjacent to the third semiconductor region and providing a channel region for the second FET; and a fifth semiconductor region of the first conductivity type adjacent to the fourth semiconductor region and providing a source/drain region for the second FET; and wherein the method further comprises forming a conductive member having a portion overlying the first trench, wherein the conductive member provides a gate for the second FET, wherein the gate for the second FET is adjacent to the channel region of the second FET. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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22. A method for fabricating an integrated circuit comprising a nonvolatile memory cell, the method comprising:
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forming a first trench in a top surface of a semiconductor substrate; forming a first dielectric on a surface of the first trench; forming a floating gate at least partially located in the first trench; and wherein the nonvolatile memory cell comprises a first field effect transistor (FET) whose conductivity is at least partially controlled by the floating gate; wherein the method further comprises forming in the substrate; a first semiconductor region of a first conductivity type adjacent to the first trench and providing a first source/drain region for the first FET; a second semiconductor region of a second conductivity type adjacent to the first trench above the first semiconductor region and providing a channel region for the first FET; a third semiconductor region of the first conductivity type, wherein at least a portion of the third semiconductor region lies adjacent to the first trench above the second semiconductor region and provides a second source/drain region for the first FET; wherein the method further comprises forming a dielectric region having at least a portion extending below the top surface of the substrate between the first trench and a top part of the third semiconductor region, wherein the third semiconductor region has a part located below said portion of the dielectric region and meeting the first trench. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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Specification