Structures of and methods of fabricating trench-gated MIS devices

• US 7,005,347 B1
• Filed: 04/27/2004
• Issued: 02/28/2006
• Est. Priority Date: 03/22/2002
• Status: Expired due to Term

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Bhalla, Anup, Lui, Sik, Pitzer, Dorman, Korec, Jacek, Shi, Xiaorong
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Ortiz, Edgardo
• Application Number:
  US10/832,776
• Time in Patent Office: 672 Days
• Field of Search: 438/243, 438/259, 438/270, 438/271, 438/386, 438/589, 257/E29.257, 257/E29.26, 257/301, 257/302, 257/330, 257/332, 257/334
• US Class Current: 438/259
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 257/905 Plural dram cells share common contact or common trench

Abstract

In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.

Claims

1. A process of fabricating an MIS device, the device comprising an active region and a termination region, comprising:

forming a trench mask over the surface of a semiconductor substrate, the substrate being doped with a material of a first conductivity type, the trench mask having an aperture defining the location of a termination trench to be formed;

etching through the aperture in the trench mask to form a termination trench in the substrate;

removing the trench mask;

forming a first nonconductive layer on a wall of the termination trench;

depositing a layer of a conductive gate material into the termination trench, the conductive gate material overflowing the surface of the substrate outside the termination trench;

etching the gate material without a mask such that a top surface of the gate material in the termination trench is reduced to a level below the surface of the substrate;

depositing a second nonconductive layer over the surface of the substrate;

forming a contact mask over the second nonconductive layer, the contact mask having a gate contact aperture;

etching the second nonconductive layer through the gate contact aperture in the contact mask to form a gate contact aperture in the second nonconductive layer;

removing the contact mask; and

depositing a second conductive layer over the second nonconductive layer, the second conductive layer extending through the gate contact aperture to make contact with the conductive gate material in the termination trench wherein said process does not include a mask for etching a portion of an oxide layer to form a field oxide region in the termination region.

2. The process of claim 1 wherein the contact mask has a substrate contact aperture, the process comprising etching the second nonconductive layer through the substrate contact aperture in the contact mask to form a substrate contact aperture in the second nonconductive layer, and wherein depositing a second conductive layer over the second nonconductive layer causes the second conductive layer to extend through the substrate contact aperture to make contact with the substrate.

3. The process of claim 2 comprising forming a metal mask over the second conductive layer, the metal mask having an aperture, and etching the second conductive layer through the aperture in the metal mask to form a first portion of the second conductive layer that is in electrical contact with the gate material and a second portion of the second conductive layer that is in electrical contact with the substrate, the first and second portions of the second conductive layer being electrically isolated from each other.

4. The process of claim 1 comprising forming a body mask over the surface of the substrate, the body mask having an aperture, and implanting dopant of a second conductivity type into the substrate through the aperture in the body mask to form a body region.

5. The process of claim 1 wherein the trench mask contains a second aperture in the active region and a third aperture in a channel stopper region, and wherein the process comprises etching the substrate through the second and third apertures to form an active trench in the active region and a channel stopper trench in the channel stopper region.

6. The process of claim 5 comprising forming a source mask over the substrate, the source mask having an aperture over an area of the substrate adjacent to the active trench, and implanting dopant of the first conductivity through the aperture in the source mask to form a source region of the MIS device.

7. The process of claim 6 wherein the source mask comprises a second aperture in the channel stopper region and the process comprises implanting dopant of the first conductivity type into an area adjacent to the channel stopper trench.

8. The process of claim 2 comprising implanting dopant of the second conductivity type through the substrate contact aperture in the second nonconductive layer to form a heavily-doped contact region in the substrate.

9. The process of claim 5 wherein

depositing a layer of conductive gate material comprises depositing the conductive gate material into the channel stopper trench;

etching the gate material without a mask comprises reducing the surface of the gate material in the channel stopper trench to a level below the surface of the substrate;

the contact mask has a second aperture over the channel stopper trench;

the process comprises etching the second nonconductive layer through the second aperture in the contact mask to expose the surface of the conductive gate material in the channel stopper trench; and

depositing the second conductive layer comprises the second conductive layer to flow into the second aperture in the contact mask and to make electrical contact with the conductive gate material in the channel stopper trench.

10. The process of claim 1 wherein:

the second conductive layer comprises metal;

the trench mask comprises a second aperture;

the process comprises etching the substrate through the second aperture in the trench mask to form a Schottky diode trench in the substrate;

depositing a layer of a conductive gate material comprises depositing the conductive gate material into the Schottky trench;

a body mask covers the Schottky trench and an adjacent area of the substrate;

the contact mask has a second aperture over an area of the substrate adjacent to the Schottky trench;

the process comprises etching the second nonconductive layer through the second aperture in the contact mask to expose the area of the substrate adjacent to the Schottky trench; and

depositing the second conductive layer comprises causing the second conductive layer to fill the second aperture in the contact mask and to make electrical contact with the area of the substrate adjacent to the Schottky trench, thereby forming a Schottky diode.

11. The process of claim 10 wherein the trench mask contains a second aperture in the active region, and wherein the process comprises etching the substrate through the second aperture to form an active trench in the active region.

12. The process of claim 11 comprising:

depositing a polysilicon layer over the substrate;

introducing a dopant of a second conductivity type into the polysilicon layer;

forming a polysilicon mask over the polysilicon layer, the polysilicon mask defining the location of a polysilicon diode to be formed;

etching an area of the polysilicon layer not covered by the polysilicon mask;

removing the polysilicon mask;

forming a source mask, the source mask having a first aperture over an area of the substrate adjacent to the trench and a second aperture over a region of the polysilicon layer; and

implanting dopant of the first conductivity type through the first and second apertures in the source mask to form a source region of the MIS device and a terminal of a polysilicon diode.

13. The process of claim 12 wherein:

depositing said second nonconductive layer is performed after implanting dopant of the first conductivity type through the first and second apertures in the source mask;

the contact mask has a cathode aperture overlying a cathode of the polysilicon diode;

the process comprises etching the second nonconductive layer through the anode and cathode apertures in the contact mask to form anode and cathode contact apertures in the second nonconductive layer, respectively; and

depositing a second conductive layer comprises causing the second conductive layer to flow into the anode and cathode contact apertures so as to make electrical contact with the anode and cathode, respectively, of the polysilicon diode.

14. The process of claim 12 wherein:

the polysilicon mask defines the location of a polysilicon MOSFET to be formed;

the trench mask contains a third aperture in the active region, the process comprising etching the substrate through the third aperture to form a polysilicon MOSFET trench; and

wherein the source mask has at least one opening defining a region within the polysilicon MOSFET.

15. The process of claim 1 comprising:

forming a second contact mask over the second nonconductive layer, the second contact mask having a substrate contact aperture;

etching the second nonconductive layer through the substrate contact aperture in the second contact mask to form a substrate contact aperture in the second nonconductive layer; and

wherein depositing a second conductive layer over the second nonconductive layer causes the second layer to extend through the substrate contact aperture to make contact with the substrate.

16. A process of fabricating an MIS device comprising:

providing a semiconductor substrate doped with a dopant of a first conductivity type;

growing an epitaxial layer of a second conductivity type on a semiconductor surface;

forming a trench mask over the surface of the epitaxial layer, the trench mask having a first aperture in an active region of the device and a second aperture in a termination region of the device, the termination region being located between the active region and a channel stopper region;

etching the epitaxial layer through the first and second apertures in the trench mask to form first and second trenches, the second trench being substantially wider than the first trench;

removing the trench mask;

forming a first nonconductive layer on a wall of the first and second trenches;

depositing a layer of a conductive gate material into the first and second trenches, the layer of conductive gate material overflowing the surface of the substrate outside the trenches;

etching the conductive gate material such that a top surface of the conductive gate material in the first trench is reduced to a level below the surface of the substrate and the conductive gate material in the second trench is substantially removed;

depositing a second nonconductive layer over the surface of the epitaxial layer and over the gate material in the first trench and into the second trench;

forming a contact mask over the second nonconductive layer, the contact mask having a substrate contact aperture and a gate contact aperture;

etching the second nonconductive layer through the apertures in the contact mask to form a substrate contact aperture and a gate contact aperture in the second nonconductive layer;

removing the contact mask; and

depositing a second conductive layer over the second nonconductive layer, the second conductive layer extending through the substrate contact aperture to make contact with the substrate and through the gate contact aperture to make contact with the conductive gate material wherein said process does not include a mask for etching a portion of an oxide layer to form a field oxide region in the termination region.

17. The process of claim 16 comprising:

forming a metal mask over the second conductive layer, the metal mask having an aperture; and

etching the second nonconductive layer through the aperture in the metal mask.