NAND flash memory cell row

• US 7,005,699 B2
• Filed: 01/15/2004
• Issued: 02/28/2006
• Est. Priority Date: 10/23/2003
• Status: Active Grant

• Current Assignee: Powerchip Semiconductor Manufacturing Corp. (Powerchip Technology Corporation)
• Original Assignee: Powerchip Semiconductor Corporation (Powerchip Technology Corporation)
• Inventors: Chen, Shih-Chang, Hsu, Cheng-Yuan, Hung, Chih-Wei
• Primary Examiner(s): TRAN, MAI HUONG C
• Application Number:
  US10/707,826
• Publication Number:
  US 20050087794A1
• Time in Patent Office: 775 Days
• Field of Search: 257/314, 257/315, 257/316, 257/321, 257/438, 438/260, 438/267, 438/254, 438/257, 438/253, 438/259
• US Class Current: 257/315
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A NAND flash memory cell row includes first and second stacked gate structures, control and floating gates, intergate dielectric layer, tunnel oxide layer, doping regions and source/drain regions. The first stacked gate structures has an erase gate dielectric layer, an erase gate and a first cap layer. The second stacked gate structure has a select gate dielectric layer, a select gate and a second cap layer. The control gate is between each of the first stacked gate structures, and between each of the second stacked gate structures and adjacent first stacked gate structure. The floating gate is between the control gate and substrate. The inter-gate dielectric layer is between the control and floating gates. The tunnel oxide is between the floating gate and substrate. The doping regions are under the first stacked gate structure, and the source/drain regions are in the exposed substrate.

Claims

1. A NAND flash memory cell row, comprising:

a substrate;

a plurality of first stacked gate structures disposed on the substrate, wherein each of the first stacked gate structures comprises an erase gate dielectric layer, an erase gate and a first cap layer;

two second stacked gate structures disposed on the substrate beside two outer sides of the first stacked gate structures respectively, wherein each of the second stacked gate structures comprises a select gate dielectric layer, a select gate and a second cap layer;

a plurality of control gates disposed between the first stacked gate structures and each of the second stacked gate structures, and between every two of the neighboring first stacked gate structures;

a plurality of floating gates disposed between the control gates and the substrate, wherein each of the floating gates has sharp corners and a concave surface facing each of the control gates, and the edge of the concave surface is lower than a top surface of the erase gate;

an inter-gate dielectric layer disposed between each of the control gates and each of the floating gates;

a tunnel oxide layer, disposed between each of the floating gates and the substrate, between each of the floating gates and the first stacked gate structures, and between each of the floating gates and the second stacked gate structures;

a plurality of doping regions disposed in the substrate under the first stacked gate structures; and

a plurality of source/drain regions disposed in the exposed substrate outside the second stacked gate structures.

2. The NAND flash memory cell row of claim 1, wherein a material of the tunnel oxide layer comprises a silicon oxide.

3. The NAND flash memory cell row of claim 1, wherein the inter-gate dielectric layer comprises a material selected from the group consisting of silicon oxide/silicon nitride/silicon oxide, silicon nitride/silicon oxide and silicon oxide/silicon nitride.

4. The NAND flash memory cell row of claim 1, wherein the first and the second cap layers comprise an oxide layer and a dielectric layer disposed on the oxide layer.

5. The NAND flash memory cell row of claim 1, wherein the NAND flash memory cell further comprising;

a p-type well region disposed in the substrate, wherein a depth of the p-type well region is deeper than a depth of the source/drain regions.