Circuit technique for high speed low power data transfer bus

• US 7,005,892 B2
• Filed: 02/20/2004
• Issued: 02/28/2006
• Est. Priority Date: 02/02/2000
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Terzioglu, Esin, Hatamian, Mehdi, Afghahi, Morteza Cyrus
• Primary Examiner(s): Tran, Anh Q.
• Application Number:
  US10/783,726
• Publication Number:
  US 20040164767A1
• Time in Patent Office: 739 Days
• Field of Search: 326 82- 83, 326/86, 326/89, 326/90, 326/112, 326/113, 326/119, 327/108, 327/112
• US Class Current: 326/86
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits

Abstract

A high speed low power data transfer bus circuit that reduces bus power consumption by imposing a limited, controlled voltage swing on the associated data bus. In one embodiment, an inverter is coupled with a pMOS pass transistor and an nMOS discharge transistor, and the combination is coupled with a data bus. The discharge transistor and pass transistor can be programmed to provide a preselected bus operational characteristics. In another embodiment, multiple nMOS discharge transistors can be coupled to the data bus via the pass transistor, with each of the discharge transistors being selectively programmed to provide additional preselected bus operational characteristics, multiple, programmable discharge transistors, thus selectably imposing encoded and multilevel logic signals on the data bus. In another embodiment, a bidirectional data transfer bus circuit couples two data busses while imposing a limited, controlled voltage swing during the transfer. One preferred embodiment couples a first data bus and a second data bus with cross-linked inverters. Interposed between the inverters, and its associated bus, is a respective pMOS pass transistor. Also, coupled between each input node and ground, is a signal discharge transistor, preferably nMOS, which facilitates data transfer between the buses. Each of the inverters is coupled with a clocked charge/discharge circuit, preferably using a common clock signal.

Claims

1. A method of controlling the voltage swing in a circuit for transferring data to a data bus, comprising:

(a) coupling a pass transistor with the bus;

(b) coupling a discharge transistor between the pass transistor and ground;

(c) coupling an inverter between the discharge transistor and the pass transistor, the inverter and the discharge transistor forming a signal node; and

(d) selectably driving the pass transistor gate with the inverter in response to a signal node voltage value.

2. The method of claim 1, further comprising programming the discharge transistor to impose a preselected bus operational characteristic on the data bus.

3. The method of claim 1, further comprising programming the pass transistor to impose a preselected bus operational characteristic on the data bus.

4. The method of claim 1, wherein coupling operation (b) comprises coupling a plurality of discharge transistors between the pass transistor and ground.

5. The method of claim 4, further comprising selectively programming ones of the plurality of discharge transistors to impose respective preselected bus operational characteristic on the data bus.

6. The method of claim 1, wherein the pass transistor couples the data bus with one of a global sense amplifier, a local sense amplifier, a global wordline decoder, and a local wordline decoder.

7. The method of claim 3, wherein the pass transistor couples the data bus with one of a global sense amplifier, a local sense amplifier, a global wordline decoder, and a local wordline decoder.

8. A method of controlling voltage swing in a data bus transfer circuit for transferring data between a first data bus and a second data bus, comprising:

(a) coupling a first pass transistor between the first data bus and a first inverter, the coupling of the first pass transistor and the first inverter forming a first signal node;

(b) coupling a second pass transistor between the second data bus and a second inverter, the coupling of the second pass transistor and the second inverter forming a second signal node;

(c) coupling a first signal discharge transistor between the first signal node and ground; and

(d) coupling a second signal discharge transistor between the first signal node and ground, wherein the first inverter transfers a signal representative of first data on the first data bus to the second signal discharge transistor and the second inverter transfers a signal representative of second data on the second data bus to the first signal discharge transistor.

9. The method of claim 8, further comprising cross-linking the second inverter to the first inverter.

10. The method of claim 8, further comprising:

(e) coupling a first node charge transistor between V_dd and the first signal node;

(f) coupling a first node discharge transistor between the first signal discharge transistor and ground;

(g) coupling a second charge transistor between the V_dd and the second signal node;

(h) coupling a second node discharge transistor between the second signal discharge transistor and ground, wherein each of the first and second node charge transistors pulls the respective first and second signal nodes to V_dd when a LOW gate signal is applied thereto.

11. The method of claim 10, further comprising operably coupling a clocking signal with the first node charge transistor, the first node discharge transistor, the second node charge transistor, and the second node discharge transistor.

12. The method of claim 8, further comprising coupling one of the first data bus and the second data bus with one of a global sense amplifier, a local sense amplifier, a global wordline decoder, and a local wordline decoder.

13. The method of claim 11, further comprising coupling one of the first data bus and the second data bus with one of a global sense amplifier, a local sense amplifier, a global wordline decoder, and a local wordline decoder.