Semiconductor memory device and method for programming and erasing a memory cell

• US 7,006,371 B2
• Filed: 11/25/2003
• Issued: 02/28/2006
• Est. Priority Date: 12/04/2002
• Status: Active Grant

• Current Assignee: Xenogenic Development Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Matsuoka, Nobuaki
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US10/722,732
• Publication Number:
  US 20040114444A1
• Time in Patent Office: 826 Days
• Field of Search: 365/46, 365/100, 365/104, 365/158, 365/148, 365/210, 365/189.04
• US Class Current: 365/148
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2013/0066 Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing
• CPC Class Codes: G11C 2211/5624 Concurrent multilevel programming and programming verification
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

A semiconductor memory device comprises a memory array in which memory cells having variable resistive elements (R₁₁ to R_ij) whose electrical resistance is varied by electrical stress and is held even after the electrical stress is released and selection transistors (T₁₁ to T_ij) comprising N type MOSFETs are arranged with a matrix; programming means for applying the electrical stress to the variable resistive elements (R₁₁ to R_ij) to program data into the memory cell; programming state detection means for detecting the variation in the electrical resistance at the time of the programming operation; and programming control means for stopping the application of the electrical stress when the electrical resistance is varied to a predetermined reference value. With this structure, it is possible to constitute the semiconductor memory device in which the time required for programming data is shortened and the programming precision is high.

Claims

1. A semiconductor memory device comprising

a memory cell having a variable resistive element whose electrical resistance is varied,

programming means for programming data into said memory cell using the variation of the electrical resistance of said variable resistive element,

programming state detection means for detecting variation in the electrical resistance at the time of programming operation carried out by said programming means, and

programming control means for stopping the programming operation by said programming means when the electrical resistance is varied to a predetermined reference value.

2. The semiconductor memory device according to claim 1 wherein said programming state detection means can detect the variation in the electrical resistance of said memory cell by comparing the electrical resistance of said memory cell with the reference value fixed to a programming reference cell.

3. The semiconductor memory device according to claim 2, wherein said programming reference cell is formed using a fixed resistance.

4. The semiconductor memory device according to claim 3, wherein said fixed resistance is formed of diffused resistor or polysilicon resistor.

5. The semiconductor memory device according to claim 1, wherein said memory cell comprises a selection transistor and a variable resistive element whose electrical resistance is varied by electrical stress and is held even after the electrical stress is released.

6. The semiconductor memory device according to claim 1, wherein said variable resistive element is formed with an oxide of perovskite structure having manganese between electrodes.

7. The semiconductor memory device according to claim 1, further comprising

erasing means for erasing data from said memory cell using variation of said electrical resistance of said variable resistive element,

erasing state detecting means for detecting variation of said electrical resistance at the time of the erasing operation by said erasing means, and

erasing control means for stopping the erasing operation by said erasing means when the electrical resistance is varied to a predetermined second reference value.

8. The semiconductor memory device according to claim 7, wherein

said programming state detection means and said erasing state detecting means are convertible to each other, and

said programming control means and said erasing control means are convertible to each other.

9. The semiconductor memory device according to claim 7, wherein said erasing state detecting means can detect the variation in the electrical resistance of said memory cell by comparing the electrical resistance with the second reference value fixed to an erasing reference cell.

10. The semiconductor memory device according to claim 9, wherein said erasing reference cell is formed using a fixed resistance.

11. The semiconductor memory device according to claim 10, wherein said fixed resistance is formed of diffused resistor or polysilicon resistor.

12. A semiconductor memory device comprising

a memory cell having a variable resistive element whose electrical resistance is varied by electrical stress and is held even after the electrical resistance is released,

programming means for programming data into said memory cell by applying the electrical stress to said variable resistive element to vary the electrical resistance,

programming state detection means for detecting variation of said electrical resistance at the time of programming operation by said programming means, and

programming control means for stopping application of the electrical stress by said programming means when the electrical resistance is varied to a predetermined reference value.

13. The semiconductor memory device according to claim 12, wherein said programming state detection means can detect the variation in the electrical resistance of said memory cell by comparing the electrical resistance with the reference value fixed to a programming reference cell.

14. The semiconductor memory device according to claim 13, wherein said programming reference cell is formed using a fixed resistance.

15. The semiconductor memory device according to claim 14, wherein said fixed resistance is formed of diffused resistor or polysilicon resistor.

16. The semiconductor memory device according to claim 12, wherein said memory cell comprises a selection transistor and a variable resistive element whose electrical resistance is varied by electrical stress and is held even after the electrical stress is released.

17. The semiconductor memory device according to claim 12, wherein said variable resistive element is formed with an oxide of perovskite structure having manganese between electrodes.

18. The semiconductor memory device according to claim 12, further comprising

erasing means for erasing data from said memory cell by applying the electrical stress to said variable resistive element to vary the electrical resistance,

erasing state detecting means for detecting variation of said electrical resistance at the time of erasing operation by said erasing means, and

erasing control means for stopping the application of electrical stress by said erasing means when the electrical resistance is varied to a predetermined second reference value.

19. The semiconductor memory device according to claim 18, wherein

said programming state detection means and said erasing state detecting means are convertible to each other, and

said programming control means and said erasing control means are convertible to each other.

20. The semiconductor memory device according to claim 18, wherein said erasing state detecting means can detect the variation in the electrical resistance of said memory cell by comparing the electrical resistance with the second reference value fixed to an erasing reference cell.

21. The semiconductor memory device according to claim 20, wherein said erasing reference cell is formed using a fixed resistance.

22. The semiconductor memory device according to claim 21, wherein said fixed resistance is formed of diffused resistor or polysilicon resistor.

23. A semiconductor memory device comprising

a memory cell having a variable resistive element whose electrical resistance is varied,

erasing means for erasing data from said memory cell using variation of the electrical resistance of said variable resistive element,

erasing state detecting means for detecting variation of the electrical resistance at the time of erasing operation by said erasing means, and

erasing control means for stopping the erasing operation by said erasing means when the electrical resistance is varied to a predetermined second reference value.

24. The semiconductor memory device according to claim 23, wherein said erasing state detecting means can detect variation of the electrical resistance of said memory cell by comparing the electrical resistance with the second reference value fixed to the erasing reference cell.

25. The semiconductor memory device according to claim 24, wherein said erasing reference cell is formed using a fixed resistance.

26. The semiconductor memory device according to claim 25, wherein said fixed resistance is formed of diffused resistor or polysilicon resistor.

27. The semiconductor memory device according to claim 23, wherein said memory cell comprises a selection transistor and a variable resistive element whose electrical resistance is varied by electrical stress and is held even after the electrical stress is released.

28. The semiconductor memory device according to claim 23, wherein said variable resistive element is formed with an oxide of perovskite structure having manganese between electrodes.

29. A semiconductor memory device comprising

a memory cell having a variable resistive element whose electrical resistance is held even after the electrical resistance is varied by electrical stress and the electrical stress is released,

erasing means for erasing data from said memory cell by applying the electrical stress to said variable resistive element to vary the electrical resistance,

erasing state detecting means for detecting variation of the electrical resistance at the time of erasing operation by said erasing means, and

erasing control means for stopping application of the electrical stress by said erasing means when the electrical resistance is varied to a predetermined second reference value.

30. The semiconductor memory device according to claim 29, wherein said erasing state detecting means can detect variation of the electrical resistance of said memory cell by comparing the electrical resistance with the second reference value fixed to an erasing reference cell.

31. The semiconductor memory device according to claim 30, wherein said erasing reference cell is formed using a fixed resistance.

32. The semiconductor memory device according to claim 31, wherein said fixed resistance is formed of diffused resistor or polysilicon resistor.

33. The semiconductor memory device according to claim 29, wherein said memory cell comprises a selection transistor and a variable resistive element whose electrical resistance is varied by electrical stress and is held even after the electrical stress is released.

34. The semiconductor memory device according to claim 29, wherein said variable resistive element is formed with an oxide of perovskite structure having manganese between electrodes.

35. A programming method into a memory cell, wherein

said memory cell includes a variable resistive element whose electrical resistance is varied,

a programming operation for programming data into said memory cell using variation of the electrical resistance and a detecting operation for detecting variation of the electrical resistance of said memory cell at the time of the programming operation are carried out simultaneously,

the programming operation is carried out until the electrical resistance reaches a predetermined reference value.

36. A programming method into a memory cell, wherein

said memory cell includes a variable resistive element whose electrical resistance is varied by electrical stress and is held even after the electrical stress is released,

a programming operation for programming data into said memory cell by applying the electrical stress to said variable resistive element to vary the electrical resistance and a detecting operation for detecting variation of the electrical resistance of said memory cell at the time of programming operation are carried out simultaneously,

the application of the electrical stress is stopped when the electrical resistance is varied to a predetermined reference value.

37. An erasing method from a memory cell, wherein

said memory cell includes a variable resistive element whose electrical resistance is varied,

an erasing operation for erasing data from said memory cell is carried out using the variation of the electrical resistance,

a detecting operation for detecting the electrical resistance of said memory cell at the time of the erasing operation is carried out simultaneously with said erasing operation,

said erasing operation is carried out until it is detected that the electrical resistance reaches a predetermined reference value.

38. An erasing method from a memory cell, wherein

said memory cell includes a variable resistive element whose electrical resistance is varied by electrical stress and is held even after the electrical stress is released,

an erasing operation for erasing data from said memory cell is carried out by applying the electrical stress to said variable resistive element to vary the electrical resistance,

a detecting operation for detecting variation of the electrical resistance of said memory cell at the time of the erasing operation, said detecting operation and said erasing operation are carried out simultaneously,

the application of the electrical stress is stopped when the electrical resistance is varied to a predetermined second reference value.