Semiconductor memory

• US 7,006,379 B2
• Filed: 03/01/2005
• Issued: 02/28/2006
• Est. Priority Date: 03/29/2001
• Status: Expired due to Term

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Goda, Akira, Noguchi, Mitsuhiro, Matsunaga, Yasuhiko
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Nguyen, Thinh T
• Application Number:
  US11/068,228
• Publication Number:
  US 20050141291A1
• Time in Patent Office: 364 Days
• Field of Search: 385/185.17, 365/185.18, 365/185.05
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor memory including a memory cell unit, the memory cell unit comprising: a plurality of memory cells in which each conductance between current terminals changes according to held data, each having a plurality of current terminals connected in series between a first terminal and a second terminal, and each capable of electrically rewriting the data; a first select switching element electrically connecting said first terminal to a data transfer line; and a MISFET serving as a second select switching element connecting said second terminal to a reference potential line, wherein said semiconductor memory has a data read mode for forcing the first and second select switching elements of said memory cell unit into conduction, applying a read voltage for forcing a path between the current terminals into conduction or cut-off according to the data of a selected memory cell, to a control electrode of the selected memory cell, applying a pass voltage for forcing a path between the current terminals into conduction irrespectively of the data of each of the memory cells other than said selected memory cell, to the control electrode of each of the memory cells other than said selected memory cell, and detecting presence and absence or magnitude of a current between said data transfer line and said reference potential line, and in said data read mode, a conductance between current terminals of said MISFET is set lower than a conductance, in the case where the conductance between the current terminals is set to be the lowest, with regards to at least one of the memory cells other than said selected memory cell.

Claims

1. A semiconductor memory including a memory cell unit, the memory cell unit comprising:

a plurality of memory cells in which each conductance between current terminals changes according to held data, each having a plurality of current terminals connected in series between a first terminal and a second terminal, and each capable of electrically rewriting the data;

a first select switching element electrically connecting said first terminal to a data transfer line; and

a second select switching element electrically connecting said second terminal to a reference potential line, wherein

said semiconductor memory has a data read mode for forcing the first and second select switching elements of said memory cell unit into conduction, applying a read voltage for forcing a path between the current terminals into conduction or cut-off according to the data of a selected memory cell, to a control electrode of the selected memory cell, applying a pass voltage for forcing a path between the current terminals into conduction irrespectively of the data of each of the memory cells other than said selected memory cell, to the control electrode of each of the memory cells other than said selected memory cell, and detecting presence and absence or magnitude of a current between said data transfer line and said reference potential line, and

in said data read mode, pass voltage nodes equal to or more than two are provided, each of said pass voltage nodes having voltages different from each other, and being electrically connected to the control electrode of the unselected memory cell between said data transfer line and said selected memory cell, and the control electrode of the unselected memory cell between said reference potential line and said selected memory cell at the same time.

2. A semiconductor memory according to claim 1, wherein

in said data read mode, a current is carried from said data transfer line to said reference potential line through said memory cell unit, a first pass voltage applied to the control electrode of an unselected memory cell between said reference potential line and said selected memory cell being set lower than a second pass voltage applied to the control electrode of the unselected memory cell between said data transfer line and said selected memory cell.

3. A semiconductor memory according to claim 1, wherein

in said data read mode, a current is carried from said reference potential line to said data transfer line through said memory cell unit, a first pass voltage applied to the control electrode of an unselected memory cell between said data transfer line and said selected memory cell being set lower than a second pass voltage applied to the control electrode of the unselected memory cell between said reference potential line and said selected memory cell.

4. A semiconductor memory according to claim 1, wherein

in said read mode, a difference between said second pass voltage and said first pass voltage is set smaller than a maximum value of an absolute value of a potential difference between said data transfer line and said reference potential line.

5. A semiconductor memory according to claim 1, comprising a memory cell array having a plurality of memory cell units connected between a plurality of data transfer lines parallel to one another and a plurality of reference potential lines crossing the plurality of data transfer lines, respectively, control electrodes of the first and second select switching elements of the plurality of memory cell units aligned in a direction of said reference potential lines being connected to first and second select control lines in common, respectively, and the control electrodes of the plurality of memory cells aligned in a direction of said data transfer lines being connected to a data control line in common, and

a conductor region short-circuiting said plurality of reference potential lines is arranged at a lower linear density than that of said data transfer lines.

6. A semiconductor memory according to claim 2, wherein

in said data read mode, a conductance between current terminals of said second select switching element is set lower than a conductance, in the case where the conductance between the current terminals of the at least one memory cell is set to be the lowest, with regards to at least one of the memory cells other than said selected memory cell.

7. A semiconductor memory according to claim 3, wherein

in said data read mode, a conductance between current terminals of said first select switching element is set lower than a conductance, in the case where the conductance between the current terminals of the at least one memory cell is set to be the lowest, with regards to at least one of the memory cells other than said selected memory cell.