Protocol and method for multi-chassis configurable time synchronization

• US 7,007,106 B1
• Filed: 05/22/2001
• Issued: 02/28/2006
• Est. Priority Date: 05/22/2001
• Status: Expired due to Term

• Current Assignee: Rockwell Technologies, LLC (Teledyne Technologies Incorporated)
• Original Assignee: Rockwell Automation Technologies Incorporated (Rockwell Automation, Inc.)
• Inventors: Zuponcic, Steven, Flood, Mark, Ruetty, Mark, Cachat, Anthony
• Primary Examiner(s): Follansbee, John
• Assistant Examiner(s): Patel, Ashok B.
• Application Number:
  US09/862,256
• Time in Patent Office: 1,743 Days
• Field of Search: 713/1, 713/2, 713/100, 713/375, 713/400, 713/401, 713/500, 713/501, 713/502, 713/600, 713/601, 714/12, 714/789, 370503-520, 702/89, 375/94, 709/248
• US Class Current: 709/248
• CPC Class Codes: H04J 3/0655 using timestamps
• CPC Class Codes: H04L 7/08 the synchronisation signals recurring cyclically

Abstract

Systems and methods are disclosed for time synchronization of operations in a control system. Synchronization networks and devices are provided for transferring synchronization information between controllers in a distributed or localized control system, which is employed in order to allow operation of such controllers to be synchronized with respect to time. Also disclosed are synchronization protocols and hardware apparatus employed in synchronizing control operations in a control system.

Claims

1. A protocol for transferring synchronization information from a first synchronization component to a second synchronization component via a network for time synchronizing operation of first and second controllers associated with the first and second synchronization components, the protocol comprising:

sending a message frame from the first synchronization component to the second synchronization component via the network, the message frame comprising time synchronization information and data;

sending an additional message frame at a fixed period, the additional message frame comprises an LCM synch bit indicating an LCM tone;

receiving the message frame and the additional message frame from the network in the second synchronization component;

synchronizing operation of the second controller with that of the first controller according to the time synchronization information; and

adjusting a timing system associated with the second controller according to the LCM synch bit.

2. The protocol of claim 1, wherein synchronizing operation of the second controller comprises adjusting the timing system associated with the second controller according to the fixed period.

3. The protocol of claim 1, the fixed period is about 50 μ

s.

4. The protocol of claim 1, further comprising sending the at least one frame comprising the LCM synch bit indicating an LCM tone periodically according to an LCM period.

5. The protocol of claim 3, the LCM period is an integer multiple of the fixed period.

6. The protocol of claim 2, the LCM period is 600 ms.

7. The protocol of claim 1, at least one frame comprises an LCM synch bit indicating an LCM tone, and synchronizer operation of the second controller comprises adjusting a timing system associated with the second controller according to the LCM synch bit.

8. The protocol of claim 1, the data comprises direct data and multiplexed data.

9. The protocol of claim 6, the amount of direct data and the amount of multiplexed data in the frame is configurable.

10. The protocol of claim 6, further comprising sending additional message frames at a fixed period, the frame comprises a direct data portion and a multiplexed data portion, the direct data comprises the direct data portion of a single frame, and the multiplexed data comprises the multiplexed data portions of a plurality of frames.

11. The protocol of claim 8, comprising presenting the direct data from the direct data portion of each frame to a host processor associated with the second synchronization component as frames are received by the second synchronization component and receiving the multiplexed data from the multiplexed data portions of a plurality of message frames.

12. The protocol of claim 9, receiving the multiplexed data from the multiplexed data portions of a plurality of message frames comprises presenting the multiplexed data to a host processor associated with the second synchronization component when the plurality of message frames has been received by the second synchronization component.

13. The protocol of claim 8, receiving the multiplexed data from the multiplexed data portions of a plurality of message frames comprises presenting the multiplexed data to a host processor associated with the second synchronization component when the plurality of message frames has been received by the second synchronization component.

14. The protocol of claim 10, comprising presenting the direct data to the host processor every 50 μ

s and presenting the multiplexed data to the host processor every 500 μ

s.

15. The protocol of claim 8, the direct data portion comprises between 0 and 4 words, and the multiplexed data portion comprises between 0 and 32 words.

16. The protocol of claim 13, the number of words in the direct data portion and the number of words in the multiplexed data portion are configurable.

17. The protocol of claim 13, the multiplexed data portion comprises between 0 and 30 words of user data and 2 words of time and configuration data.

18. The protocol of claim 8, the multiplexed data portion comprises between 0 and 30 words of user data and 2 words of time and configuration data.

19. The protocol of claim 16, the time and configuration data comprises at least one of a configuration ID portion, a status portion, a CST sequence count portion, a CST value portion, an offset portion, and a time master ID portion.

20. The protocol of claim 17, the sizes of the direct data portion and the multiplexed data portion are determined according to the configuration ID portion.

21. The protocol of claim 1, further comprising sending a plurality of frames at a fixed period using data flooding, at least a portion of the data is sent in more than one frame.

22. The protocol of claim 1, the first and second synchronization components are configured together with other synchronization components in at least one of a star topology, a daisy-chain topology, and a loop topology.

23. The protocol of claim 20, the data is presented to host processors individually associated with the synchronization components simultaneously in all the synchronization components.

24. The protocol of claim 20, the synchronization components are configured in a star topology, and the data comprises direct data and multiplexed data.

25. The protocol of claim 20, the synchronization components are configured in a daisy-chain topology, and the data comprises direct data.

26. The protocol of claim 1, the frame comprises three flag bytes, a control byte, a data field, and two CRC bytes.

27. The protocol of claim 24, the data field comprises 6 32 bit words.

28. The protocol of claim 24, control byte comprises a sequence count, a multiplier overflow bit, and an LCM synch bit.

29. The protocol of claim 26, the data field comprises a multiplexed data portion, the multiplexed data portion comprises a portion of multiplexed data being sent in a plurality of frames, and the sequence count is indicative of the portion of the multiplexed data being sent in the current frame.