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Digital signal processor for wireless baseband processing

  • US 7,007,155 B2
  • Filed: 09/17/2002
  • Issued: 02/28/2006
  • Est. Priority Date: 09/17/2001
  • Status: Active Grant
First Claim
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1. A wireless baseband processing circuit, comprising:

  • a first linear array of reconfigurable processing elements for processing signals from a first channel;

    a second linear array of reconfigurable processing elements, coupled in parallel with the first linear array of reconfigurable processing elements, for processing signals from a second channel that is concurrent with the first channel;

    a frame buffer army having a number of frame buffers that corresponds to a number of reconfigurable processing elements in the first and second linear arrays of processing elements;

    a point-to-point data bus connected between each reconfigurable processor and an associated frame buffer; and

    a shared data bus connected between the first and second linear arrays of reconfigurable processing elements and the frame buffer array.

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