Digital signal processor for wireless baseband processing

• US 7,007,155 B2
• Filed: 09/17/2002
• Issued: 02/28/2006
• Est. Priority Date: 09/17/2001
• Status: Active Grant

• Current Assignee: Nytell Software LLC (Intellectual Ventures LLC)
• Original Assignee: Morpho Technologies
• Inventors: Mohebbi, Behzad Barjesteh, Kurdahi, Fadi Joseph
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US10/246,366
• Publication Number:
  US 20030108119A1
• Time in Patent Office: 1,260 Days
• Field of Search: 712/35, 712/10, 712/15, 712/225
• US Class Current: 712/35
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses

Abstract

A circuit employing an array of reconfigurable processing elements for wireless baseband processing. The circuit includes a first linear array of reconfigurable processing elements for processing signals from a first channel, and a second linear array of reconfigurable processing elements, coupled in parallel with the first linear array of reconfigurable processing elements, for processing signals from a second channel that is concurrent with the first channel. The circuit also includes a frame buffer array having a number of frame buffers that corresponds to a number of reconfigurable processing elements in the first and second linear arrays of processing elements. A point-to-point data bus is connected between each reconfigurable processor and an associated frame buffer. A shared data bus is connected between the first and second linear arrays of reconfigurable processing elements and the frame buffer array.

Claims

1. A wireless baseband processing circuit, comprising:

a first linear array of reconfigurable processing elements for processing signals from a first channel;

a second linear array of reconfigurable processing elements, coupled in parallel with the first linear array of reconfigurable processing elements, for processing signals from a second channel that is concurrent with the first channel;

a frame buffer army having a number of frame buffers that corresponds to a number of reconfigurable processing elements in the first and second linear arrays of processing elements;

a point-to-point data bus connected between each reconfigurable processor and an associated frame buffer; and

a shared data bus connected between the first and second linear arrays of reconfigurable processing elements and the frame buffer array.

2. The circuit of claim 1, further comprising a context memory connected to the first and second linear arrays of reconfigumble processing elements.

3. The circuit of claim 2, further comprising a reduced instruction set computer processor connected to control the context memory.

4. The circuit of claim 3, further comprising:

a direct memory access controller

a code generator; and

an interleaver,

wherein the direct memory access controller, the code generator, and the interleaver are responsive to the reduced instruction set computer processor for controlling the first and second arrays of reconfigurable processing elements.

5. The circuit of claim 1, wherein the frame buffer array is interleaved with the first and second linear arrays of reconfigurable processing elements.

6. A wireless baseband processing circuit, comprising:

a first set of linear arrays of reconfigurable processing elements for processing signals from a first channel;

a second set of linear arrays of reconfigurable processing elements for processing signals from a second channel that is concurrent with the first channel;

a frame buffer array having a number of frame buffers that corresponds to a number of reconfigurable processing elements in the first and second sets of linear arrays of processing elements, wherein the frame buffer array is interleaved with the first and second sets of linear arrays of reconfigurable processing elements;

a point-to-point data bus connected between each reconfigurable processor and an associated frame buffer; and

a shared data bus connected between the first and second sets of linear arrays of reconfigurable processing elements and the frame buffer array.

7. The circuit of claim 6, wherein each frame buffer includes one or more frame buffer cells.

8. The circuit of claim 6, further comprising a context memory connected to the first and second linear arrays of reconfigurable processing elements.

9. The circuit of claim 8, further comprising a reduced instruction set computer processor connected to control the context memory.

10. The circuit of claim 9, further comprising:

a direct memory access controller;

a code generator; and

an interleaver,

wherein the direct memory access controller, the code generator, and the interleaver are responsive to the reduced instruction set computer processor for controlling the first and second arrays of reconfigurable processing elements.

11. A wireless baseband processing circuit comprising:

a plurality of reconfigurable processing elements arranged in a two-dimensional array and connected together by a first data bus arrangement;

a plurality of frame buffers arranged in the two-dimensional array and connected together by the first data bus arrangement,

wherein each reconfigurable processing element is connected to a frame buffer in a third dimension by a second data bus arrangement.

12. The circuit of claim 11, wherein the first data bus arrangement includes a plurality of shared two-dimensional data busses.

13. The circuit of claim 12, wherein the second data bus includes a plurality of point-to-point data busses.

14. The circuit of claim 13, wherein the second data bus arrangement is configured for bulk data transfer between the plurality of reconfigurable processing elements and the plurality of frame buffers.

15. The circuit of claim 11, further comprising a context memory connected to the two-dimensional array of reconfigurable processing elements.

16. The circuit of claim 15, further comprising a reduced instruction set computer processor connected to control the context memory.

17. The circuit of claim 16, further comprising:

a direct memory access controlled;

a code generator; and

an interleaver,

wherein the direct memory access controller, the code generator, and the interleaver are responsive to the reduced instruction set computer processor for controlling the first and second arrays of reconfigurable processing elements.