Precision bypass clock for high speed testing of a data processor
First Claim
1. For use in an integrated circuit operating from a high-speed reference clock signal, a system clock circuit for providing said high-speed reference clock signal to said integrated circuit comprising:
- a frequency combiner circuit capable of receiving a first external clock signal having a frequency F1 and a second external clock signal having frequency F2, where F2 is an integer multiple of F1, wherein said second external clock signal is phase-shifted by P degrees with respect to said first external clock signal, and wherein said frequency combiner circuit generates from said first and second external clock signals a first output clock signal having an operating frequency that is the sum of F1 and F2; and
a clock selection circuit capable of selectively applying said first output clock signal to said integrated circuit.
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Accused Products
Abstract
A system clock circuit that provides a high-speed reference clock signal for operating an integrated circuit. The system clock circuit comprises a frequency combiner circuit that receives a first external clock signal having a frequency F1 and a second external clock signal having frequency F2, where F2 is an integer multiple of F1. The second external clock signal is phase-shifted by P degrees with respect to the first external clock signal. The frequency combiner circuit generates from the first and second external clock signals a first output clock signal having an operating frequency that is the sum of F1 and F2. The system clock circuit also comprises a clock selection circuit that selectively applies the first output clock signal to the integrated circuit.
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Citations
22 Claims
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1. For use in an integrated circuit operating from a high-speed reference clock signal, a system clock circuit for providing said high-speed reference clock signal to said integrated circuit comprising:
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a frequency combiner circuit capable of receiving a first external clock signal having a frequency F1 and a second external clock signal having frequency F2, where F2 is an integer multiple of F1, wherein said second external clock signal is phase-shifted by P degrees with respect to said first external clock signal, and wherein said frequency combiner circuit generates from said first and second external clock signals a first output clock signal having an operating frequency that is the sum of F1 and F2; and a clock selection circuit capable of selectively applying said first output clock signal to said integrated circuit. - View Dependent Claims (2, 3, 4, 5)
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6. For use in an integrated circuit operating from a high-speed reference clock signal, a system clock circuit for providing said high-speed reference clock signal to said integrated circuit comprising:
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a frequency combiner circuit capable of receiving N external clock signals, wherein each of said N external clock signals has a frequency that is an integer multiple of a fundamental one of said N external clock signals and each of said N external clock signals is phase-shifted with respect to said fundamental external clock signal, and wherein said frequency combiner circuit generates from said N external clock signals a first output clock signal having an operating frequency that is the sum of the frequencies of said N external clock signals; and a clock selection circuit capable of selectively applying said first output clock signal to said integrated circuit. - View Dependent Claims (7, 8, 9, 10, 11)
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12. An integrated circuit comprising:
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a processor core; a memory; a plurality of peripheral devices; and an internal bus for transferring data between said processor core, said memory and said peripheral devices; a system clock circuit for providing a high-speed reference clock signal to said processor core, said memory and said peripheral devices, said system clock circuit comprising; a frequency combiner circuit capable of receiving N external clock signals, wherein each of said N external clock signals has a frequency that is an integer multiple of a fundamental one of said N external clock signals and each of said N external clock signals is phase-shifted with respect to said fundamental external clock signal, and wherein said frequency combiner circuit generates from said N external clock signals a first output clock signal having an operating frequency that is the sum of the frequencies of said N external clock signals; and a clock selection circuit capable of selectively applying said first output clock signal to said integrated circuit. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A method of providing a high-speed reference clock signal to an integrated circuit comprising the steps of:
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applying to the inputs of a frequency combiner circuit N external clock signals, wherein each of the N external clock signals has a frequency that is an integer multiple of a fundamental one of the N external clock signals and each of the N external clock signals is phase-shifted with respect to the fundamental external clock signal; in the frequency combiner circuit, generating from the N external clock signals a first output clock signal having an operating frequency that is the sum of the frequencies of the N external clock signals; and selectively applying the first output clock signal to the integrated circuit. - View Dependent Claims (19, 20, 21, 22)
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Specification