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Precision bypass clock for high speed testing of a data processor

  • US 7,007,188 B1
  • Filed: 04/29/2003
  • Issued: 02/28/2006
  • Est. Priority Date: 04/29/2003
  • Status: Expired due to Fees
First Claim
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1. For use in an integrated circuit operating from a high-speed reference clock signal, a system clock circuit for providing said high-speed reference clock signal to said integrated circuit comprising:

  • a frequency combiner circuit capable of receiving a first external clock signal having a frequency F1 and a second external clock signal having frequency F2, where F2 is an integer multiple of F1, wherein said second external clock signal is phase-shifted by P degrees with respect to said first external clock signal, and wherein said frequency combiner circuit generates from said first and second external clock signals a first output clock signal having an operating frequency that is the sum of F1 and F2; and

    a clock selection circuit capable of selectively applying said first output clock signal to said integrated circuit.

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