Use of conductive electrolessly deposited etch stop layers, liner layers and via plugs in interconnect structures

• US 7,008,872 B2
• Filed: 05/03/2002
• Issued: 03/07/2006
• Est. Priority Date: 05/03/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Dubin, Valery M., Hussein, Makarem, Cheng, Chin-Chang, Nguyen, Phi L., Brain, Ruth A.
• Primary Examiner(s): Nguyen, Tuan H.
• Assistant Examiner(s): Dolan, Jennifer M
• Application Number:
  US10/139,052
• Publication Number:
  US 20030207560A1
• Time in Patent Office: 1,404 Days
• Field of Search: 438/687, 438/678, 438/624, 438/625, 438622-629, 438/631, 438/634, 438636-640, 438/641, 438/643, 438/660
• US Class Current: 438/678
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 21/76868 Forming or treating discontinuous thin films, e.g. repair, enhancement or reinforcement of discontinuous thin films
• CPC Class Codes: H01L 21/76874 for electroless plating
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interconnect line formed over the via. Often the metal layer contains a cobalt or nickel alloy and provides an etch stop layer for formation of an opening corresponding to the via. The metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer. The metal layer is conductive, rather than dielectric, and provides a shunt for passage of electrical current between the via and the interconnect line. Similar metal layers may also be used within the interconnect structures as via liner layers and via plugs.

Claims

1. A method comprising

recessing an interconnect line relative to a dielectric layer in which the interconnect line is disposed by selectively removing material of the interconnect line relative to material of the dielectric layer;

electrolessly depositing a conductive material over the recessed interconnect line; and

annealing the electrolessly deposited conductive material by heating in an atmosphere including a trace amount of oxygen.

2. A method comprising

recessing an interconnect line relative to a dielectric layer in which the interconnect line is disposed by selectively removing material of the interconnect line relative to material of the dielectric layer;

electrolessly depositing a conductive material over the recessed interconnect line; and

cleaning a surface of the electrolessly deposited conductive material by contacting the surface with a cleanser including an etching agent.

3. The method of claim 2, wherein said removing the material of the interconnect line comprises etching the material of the interconnect line.

4. The method of claim 3, wherein said etching the material comprises etching the material with an etching agent during a post-planarization cleaning operation.

5. The method of claim 2, wherein said cleaning the surface comprises contacting the surface with a cleanser including one or more etching agents selected from acids and oxidizers.

6. The method of claim 2, wherein said cleaning the surface comprises contacting the surface with a cleanser comprising one or more of a surfactant and an alcohol to help wet the surface.

7. The method of claim 2, wherein said cleaning the surface comprises contacting the surface with an aqueous solution including one or more selected from surfactants and alcohols to help wet the surface and one or more etching agents selected from acids and oxidizers.

8. A method comprising

electrolessly depositing a conductive material over an interconnect structure that is disposed within a dielectric layer;

cleaning a surface of the conductive material by contacting the surface with a cleanser including an etching agent to etch the electrolessly deposited conductive material; and

after said cleaning, annealing the electrolessly deposited conductive material by heating the electrolessly deposited conductive material in an atmosphere including a trace amount of oxygen.

9. A method comprising:

electrolessly depositing a conductive material over an interconnect structure that is disposed within a dielectric layer; and

annealing the electrolessly deposited conductive material by heating the electrolessly deposited conductive material in an atmosphere including a trace amount of oxygen.

10. The method of claim 9, wherein said annealing comprises heating the electrolessly deposited conductive material to a temperature of about 450°

C.

11. The method of claim 9, wherein said annealing comprises heating the electrolessly deposited conductive material in an inert atmosphere.

12. The method of claim 9, wherein said annealing comprises heating the electrolessly deposited conductive material in a reducing atmosphere.

13. The method of claim 9, further comprising, prior to said annealing, cleaning a surface of the electrolessly deposited conductive material by contacting the surface with a cleanser including an etching agent to etch the electrolessly deposited conductive material.

14. The method of claim 9, further comprising depositing a second dielectric layer over the dielectric layer and over the annealed electrolessly deposited conductive material.

15. A method comprising:

electrolessly depositing a via plug in an opening formed in a dielectric layer, wherein the opening is at least partially over a first interconnect line, wherein the via plug includes one or more of boron and phosphorous;

electrolessly depositing a liner layer on the electrolessly deposited via plug, wherein the liner layer includes a greater total concentration of boron and phosphorous than the via plug; and

forming a second interconnect line on the electrolessly deposited liner layer.

16. The method of claim 15,

wherein said electrolessly depositing the via plug comprises electrolessly depositing a composition including less than 10 atomic percent phosphorous and less than 5 atomic percent boron;

and

wherein said electrolessly depositing the liner layer comprises electrolessly depositing a composition including more than 10 atomic percent phosphorous and more than 5 atomic percent boron.