High-sensitivity optical scanning using memory integration

• US 7,009,163 B2
• Filed: 06/21/2002
• Issued: 03/07/2006
• Est. Priority Date: 06/22/2001
• Status: Expired due to Fees

• Current Assignee: Orbotech Limited (KLA Corporation)
• Original Assignee: Orbotech Limited (KLA Corporation)
• Inventors: Katzir, Yigal, Gur-Arie, Itay, Malinovich, Yacov
• Primary Examiner(s): Luu, Thanh X.
• Assistant Examiner(s): Sohn, Seung C.
• Application Number:
  US10/176,003
• Publication Number:
  US 20030006364A1
• Time in Patent Office: 1,355 Days
• Field of Search: 250/208.1, 250/550, 250/205, 250/234, 250/226, 250/214.A, 250/214.DC, 348/88, 348/92, 382/147, 382/149
• US Class Current: 250/208.1
• CPC Class Codes: G01N 21/8851 Scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment, for detecting different kinds of defects, for compensating for structures, markings, edges G01N21/8806 and G01N21/93 - G01N21/95692 take precedence; optical measurement of dimensions G01B11/00; optical scanning G02B26/10; image transformation G06T3/00; computerised image enhancement G06T5/00; image processing per se for flaw detection G06T7/0002
• CPC Class Codes: G01N 21/8901 Optical details; Scanning details per se G02B
• CPC Class Codes: G01N 21/956 Inspecting patterns on the surface of objects contactless testing of electronic circuits G01R31/308; testing currency G07D; manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H04N 25/46 by combining or binning pixels
• CPC Class Codes: H04N 25/768 for time delay and integration [TDI]
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

An inspection system includes a CMOS integrated circuit having integrally formed thereon an at least two dimensional array of photosensors and providing an inspection output representing an object to be inspected. A defect analyzer is operative to receive the inspection output and to provide a defect report.

Claims

1. An inspection system comprising:

a CMOS integrated circuit having integrally formed thereon an at least two dimensional array of photosensors and providing a plurality of two-dimensional outputs representing an object to be inspected, said plurality of outputs including at least a first image frame and a second image frame, said first image frame obtained by simultaneous detection of a two dimensional portion of said object by a plurality of lines of said array of photosensors and said second image frame subsequently obtained by simultaneous detection of a two dimensional portion of said object by a plurality of lines of said array of photosensors; and

a defect analyzer utilizing said plurality of outputs to detect defects in said object.

2. The inspection system claimed in claim 1 and further comprising a scanner having a support assembly supporting said object to be inspected and wherein said CMOS integrated circuit is operative to acquire a plurality of images of said object during scanning thereof, said CMOS integrated circuit providing said images as two dimensional outputs.

3. The inspection system claimed in claim 2 further comprising a plurality of A/D converters outside said two dimensional array of photosensors operative to digitize said plurality of images to provide said plurality of outputs.

4. The inspection system claimed in claim 2 and wherein said plurality of images comprises a first plurality of images associated with a first color spectrum and a second plurality of images associated with a second color spectrum.

5. The inspection system claimed in claim 2 and wherein each image in said plurality of images at least partially overlaps another image in said plurality of images.

6. The inspection system claimed in claim 5 and further comprising a composite image generator situated outside said array of photosensors operative to receive said plurality of two-dimensional outputs and generate a composite image of said object by combining said plurality of two-dimensional outputs.

7. The inspection system claimed in claim 6 and further comprising an image analyzer analyzing said composite image to determine defects in said object.

8. The inspection system claimed in claim 7 and wherein said object is an electrical circuit.

9. The inspection system claimed in claim 6, wherein said composite image generator is operative to receive and combine digital values corresponding to said two-dimensional outputs.

10. The inspection system claimed in claim 9, further comprising a memory storing digital image data, said digital image data comprising digital values combined outside said two dimensional array of photosensors.

11. The inspection system claimed in claim 6, wherein said composite generator is operative to combine digital values from a sequentially acquired two-dimensional output with previously stored image data, to generate a composite image of said object.

12. The inspection system claimed in claim 5 and further comprising an illumination assembly generally continuously illuminating said object to be inspected and wherein said CMOS integrated circuit is operative to acquire said plurality of images during illumination of said object.

13. The inspection system claimed in claim 5, wherein said plurality of images are sequentially acquired.

14. The inspection system claimed in claim 2 and wherein each image in said plurality of images at least partially overlaps another image in said plurality of images by a single row of pixels generated by said at least two dimensional array of photosensors.

15. The inspection system claimed in claim 2 and further comprising an illumination assembly generally continuously illuminating said object to be inspected and wherein said CMOS integrated circuit is operative to acquire said plurality of images during illumination of said object.

16. The inspection system claimed in claim 2 and wherein said CMOS integrated circuit has integrally formed thereon, in addition to said at least two dimensional array of photo sensors, at least one A/D converter receiving outputs from said at least two dimensional array of photosensors.

17. The inspection system claimed in claim 16 and wherein said at least one A/D converter comprises an A/D converter associated with each photosensor in said array.

18. The inspection system claimed in claim 16 and wherein said at least one A/D converter comprises an A/D converter associated with a plurality of said photosensors.

19. The inspection system claimed in claim 16 and further comprising a plurality of digital registers outside said two dimensional array of photosensors temporarily storing the outputs of said A/D converters.

20. The inspection system claimed in claim 19 and wherein said CMOS integrated circuit has integrally formed thereon at least one additional device selected from a group including the following:

a plurality of A/D converters digitizing said plurality of two dimensional outputs;

a composite image generator combining said plurality of images;

a digital memory storing image data provided by said array of photosensors; and

a plurality of digital adders adding the outputs of said plurality of digital registers to corresponding image data stored in said digital memory.

21. The inspection system claimed in claim 20 and wherein said digital memory comprises an array of digital memory cells.

22. The inspection system claimed in claim 20 and wherein said CMOS integrated circuit comprises timing circuitry associated with said array of photosensors, said adders and said digital memory, said timing circuitry generating a sequence of clock cycles.

23. The inspection system claimed in claim 22 and wherein said CMOS integrated circuit comprises:

an input pointer indicating at each clock cycle a location in said digital memory at which to add an output of said at least one A/D converters; and

an output pointer indicating at each clock cycle a location in said digital memory from which to retrieve said image data.

24. The inspection system claimed in claim 23 and wherein said timing circuitry is operative to change a location of said input pointer and to change a location of said output pointer at each clock cycle.

25. The inspection system claimed in claim 1 and further comprising an illumination assembly generally continuously illuminating said object to be inspected and wherein said CMOS integrated circuit is operative to acquire multiple images of said object during illumination thereof.

26. A method for manufacturing electrical circuits comprising:

depositing a portion of an electrical circuit on a substrate in a given pattern; and

optically inspecting said portion to determine defects in said portion using an inspection system comprising;

a CMOS integrated circuit having integrally formed thereon an at least two dimensional array of photosensors and providing a plurality of two-dimensional outputs representing an electrical circuit to be inspected, said plurality of outputs including at least a first image frame and a second image frame, said first image frame obtained by simultaneous detection of a two dimensional portion of said electrical circuit by a plurality of lines of said array of photosensors and said second image frame subsequently obtained by simultaneous detection of a two dimensional portion of said object by a plurality of lines of said array of photosensors; and

a defect analyzer utilizing said plurality of outputs to detect defects in said electrical circuit.

27. The method claimed in claim 26 and wherein:

said inspection system further comprises a scanner having a support assembly supporting said electrical circuit to be inspected; and

said CMOS integrated circuit is operative to acquire a plurality of images of said electrical circuit during scanning thereof, said CMOS integrated circuit providing said images as two dimensional outputs.

28. The method claimed in claim 27 and wherein said inspection system further comprises a plurality of A/D converters outside said two dimensional array of photosensors operative to digitize said plurality of images.

29. The method claimed in claim 27 and wherein said plurality of images comprises a first plurality of images associated with a first color spectrum and a second plurality of images associated with a second color spectrum.

30. The method claimed in claim 27 and wherein each image in said plurality of images at least partially overlaps another image in said plurality of images.

31. The method claimed in claim 30 and wherein:

said inspection system further comprises an illumination assembly generally continuously illuminating said electrical circuit to be inspected; and

said CMOS integrated circuit is operative to acquire said plurality of images during illumination of said electrical circuit.

32. The method claimed in claim 30, wherein said plurality of images are sequentially acquired.

33. The method claimed in claim 27 and wherein each image in said plurality of images at least partially overlaps another image in said plurality of images by a single row of pixels generated by said at least two dimensional array of photosensors.

34. The method claimed in claim 27 and wherein:

said inspection system further comprises an illumination assembly generally continuously illuminating said electrical circuit to be inspected; and

said CMOS integrated circuit is operative to acquire said plurality of images during illumination of said electrical circuit.

35. The method claimed in claim 27 and wherein said CMOS integrated circuit has integrally formed thereon, in addition to said at least two dimensional array of photosensors, at least one A/D converter receiving outputs from said at least two dimensional array of photosensors.

36. The method claimed in claim 35 and wherein said at least one A/D converter comprises an A/D converter associated with each photosensor in said array.

37. The method claimed in claim 35 and wherein said at least one A/D converter comprises an A/D converter associated with a plurality of said photosensors.

38. The method claimed in claim 35 and wherein said CMOS integrated circuit has additionally integrally formed thereon a plurality of digital registers temporarily storing the outputs of said A/D converters.

39. The method claimed in claim 38 and wherein said CMOS integrated circuit has integrally formed thereon at least one additional device selected from a group including the following:

a plurality of A/D converters digitizing said plurality of two dimensional outputs;

a composite image generator combining said plurality of images;

a digital memory storing image data provided by said array of photosensors; and

a plurality of digital adders adding the outputs of said plurality of digital registers to corresponding image data stored in said digital memory.

40. The method claimed in claim 39 and wherein said digital memory comprises an array of digital memory cells.

41. The method claimed in claim 39 and wherein said CMOS integrated circuit comprises timing circuitry associated with said array of photosensors, said adders and said digital memory, said timing circuitry generating a sequence of clock cycles.

42. The method claimed in claim 41 and wherein said CMOS integrated circuit includes:

an input pointer indicating at each clock cycle a location in said digital memory at which to add an output of said at least one A/D converters; and

an output pointer indicating at each clock cycle a location in said digital memory from which to retrieve said image data.

43. The method claimed in claim 42 and wherein said timing circuitry is operative to change a location of said input pointer and to change a location of said output pointer at each clock cycle.

44. The method claimed in claim 26 and wherein said optically inspecting further comprises generating a composite image of said electrical circuit by combining said plurality of two dimensional outputs in a composite image generator situated outside said array of photosensors.

45. The method claimed in claim 44, wherein said generating a composite image comprises receiving and combining digital values corresponding to said plurality of two-dimensional outputs.

46. The method claimed in claim 45, wherein said inspection system further comprises a memory storing digital image data, said digital image data comprising digital values combined outside said two dimensional array of photosensors.

47. The method claimed in claim 44, wherein said composite generator is operative to combine digital values from a sequentially acquired two-dimensional output with previously stored image data, to generate a composite image of said object.

48. The method claimed in claim 26 and wherein:

said inspection system further comprises an illumination assembly generally continuously illuminating said electrical circuit to be inspected; and

said CMOS integrated circuit is operative to acquire multiple images of said electrical circuit during illumination thereof.