Semiconductor device with a cavity therein and a method of manufacturing the same

• US 7,009,273 B2
• Filed: 09/19/2003
• Issued: 03/07/2006
• Est. Priority Date: 09/19/2002
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Mizushima, Ichiro, Sato, Tsutomu, Matsuda, Satoshi, Inoh, Kazumi, Ishiuchi, Hidemi
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Mandala, Victor A.
• Application Number:
  US10/665,614
• Publication Number:
  US 20040129998A1
• Time in Patent Office: 900 Days
• Field of Search: 257/499, 257/506, 257/522
• US Class Current: 257/522
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0218 of field effect structures
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 12/0387 Making the trench
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device includes a semiconductor substrate, cavities, and an element isolating region. The cavities, which are each shaped like a flat plate, are made in the semiconductor substrate. The element isolating region is formed in the surface of the semiconductor substrate and located at the sides of the cavities.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a flat-plate-shaped cavity made in the semiconductor substrate; and

an element isolating region formed in the surface of the semiconductor substrate and located at the sides of the cavity, the cavity being wider than an element region provided on the cavity;

wherein the element isolating region is less deep than the cavity and deeper than the element region.

2. The semiconductor device according to claim 1, wherein the element isolating region and the cavity enclose the element region and electrically separate the element region from the semiconductor substrate.

3. The semiconductor device according to claim 1, wherein only one element region is provided on the cavity.

4. The semiconductor device according to claim 1, wherein the element isolating region is formed of an oxide film obtained by oxidizing the semiconductor substrate.

5. The semiconductor device according to claim 1, wherein the cavity has no element therein.

6. The method according to claim 1, wherein the cavity has no element therein.

7. A semiconductor device comprising:

a semiconductor substrate;

a plurality of flat-plate-shaped cavities made in the semiconductor substrate; and

an element isolating region formed in the surface of the semiconductor substrate between adjacent ones of the cavities, a part of the element isolating region being exposed to the cavities, each cavity being wider than each element region provided on each cavity, respectively;

wherein the element isolating region is less deep than the cavities and deeper than the element region.

8. The semiconductor device according to claim 7, wherein the element isolating region and the cavities enclose the element regions and electrically separate the element regions from the semiconductor substrate.

9. The semiconductor device according to claim 7, wherein only one element region is provided on the cavity.

10. The semiconductor device according to claim 7, wherein the element isolating region is formed of an oxide film obtained by oxidizing the semiconductor substrate.

11. The semiconductor device according to claim 7, wherein the cavity has no element therein.

12. A method of fabricating a semiconductor device, comprising:

making flat-plate-shaped cavities partly in a semiconductor substrate;

forming an insulating film in the surface of the semiconductor substrate between adjacent ones of the cavities in such a manner that a part of the insulating film is exposed to the cavities so as to electrically separate element regions provided on the cavities from each other, each cavity being wider than each element region; and

forming semiconductor elements on the element regions;

wherein the insulating film is less deep than the cavities and deeper than the element region.

13. The method according to claim 12, wherein the insulating film is formed by oxidizing the surface of the semiconductor substrate.

14. The method according to claim 12, wherein the insulating film and the cavities enclose the element regions and electrically separate the element regions from the semiconductor substrate.

15. The method according to claim 12, wherein only one element region provided on each of the cavities.