Massively parallel interface for electronic circuit

• US 7,009,412 B2
• Filed: 08/12/2004
• Issued: 03/07/2006
• Est. Priority Date: 05/27/1999
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: NanoNexus, Inc.
• Inventors: Chong, Fu Chiung, Mok, Sammy
• Primary Examiner(s): HOLLINGTON, JERMELE M
• Application Number:
  US10/918,511
• Publication Number:
  US 20050051353A1
• Time in Patent Office: 572 Days
• Field of Search: 324/754, 324/755, 324/760, 324/765, 324/767
• US Class Current: 324/754.14
• CPC Class Codes: G01R 1/06722 Spring-loaded
• CPC Class Codes: G01R 1/07342 the body of the probe being at an angle other than perpendicular to test object, e.g. probe card
• CPC Class Codes: G01R 3/00 Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments , e.g. of probe tips
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04
• CPC Class Codes: G01R 31/2874 related to temperature
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence

Abstract

Several embodiments of massively parallel interface structures are disclosed, which may be used in a wide variety of permanent or temporary applications, such as for interconnecting integrated circuits (ICs) to test and burn-in equipment, for interconnecting modules within electronic devices, for interconnecting computers and other peripheral devices within a network, or for interconnecting other electronic circuitry. Preferred embodiments of the massively parallel interface structures provide massively parallel integrated circuit test assemblies. The massively parallel interface structures preferably use one or more substrates to establish connections between one or more integrated circuits on a semiconductor wafer, and one or more test modules. One or more layers on the intermediate substrates preferably include MEMS and/or thin-film fabricated spring probes. The parallel interface assemblies provide tight signal pad pitch and compliance, and preferably enable the parallel testing or burn-in of multiple ICs, using commercial wafer probing equipment. In some preferred embodiments, the parallel interface assembly structures include separable standard electrical connector components, which reduces assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form.

Claims

1. An apparatus for providing simultaneous electrical connections from an integrated circuit tester to an array of integrated circuit dice on a wafer, comprising:

a plurality of interface modules, each of said interface modules comprising means for making simultaneous electrical connections to said dice;

each of said interface modules further comprising a first planar region at a first end and a second planar region which extends said first end to a second end opposite said first end, said interface module comprising a plurality of electrically conductive pads disposed on sold first planar region for providing electrical connections to pads on said dice; and

an interconnection link for providing an electrical connection to said tester at said second end and at least one electrical connection extending from at least one of said electrically conductive pads to said interconnection link; and

a substrate having a probe surface and a connector surface, said probe surface having a plurality of probe contact tips for making simultaneous electrical contact to electrical contact pads of each of said integrated circuit dice, and a plurality of connections extending through said substrate between each of said plurality of said contact tips and said connector surface for interconnection with said electrically conducting pads;

wherein said probe contact tips comprise a stress metal spring.

2. The apparatus of claim 1, wherein an average connection density of said electrically conductive pads disposed on said first planar region of said interface module is equal to or greater than an average pad density of said dice.

3. The apparatus of claim 1, each of said interface modules further comprising:

a power control module; and

at least one buss bar in electrical connection therewith.

4. The apparatus of claim 1, further comprising:

means for holding each of said plurality of interface modules in physical alignment with said dice and for making simultaneous electrical connections to the pads of each die.

5. The apparatus of claim 1, further comprising at least one interposer.

6. The apparatus of claim 1, said probe contact tips comprising structures fabricated in a batch mode processes, comprising any of thin film microelectronic mechanical system processes.