Single supply level shifter

• US 7,009,424 B2
• Filed: 06/10/2004
• Issued: 03/07/2006
• Est. Priority Date: 06/10/2004
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Khan, Qadeer A., Wadhwa, Sanjay K., Misri, Kulbhushan
• Primary Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US10/865,269
• Publication Number:
  US 20050275429A1
• Time in Patent Office: 635 Days
• Field of Search: 326/81, 326/68, 327/333
• US Class Current: 326/81
• CPC Class Codes: H03K 3/356008 ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

A level shifter that shifts a low supply voltage input signal to a higher supply voltage output signal includes a first unit and a second unit. The first unit is connected to a high power supply voltage source and receives the input signal. The first unit acts as a startup circuit such that when the level shifter is switched on, the first unit discharges an output node if the input signal is a logic low, and when the input signal is a logic high, the first unit charges a control node to the voltage of the input signal. The second unit is connected to the first unit and the high power supply voltage source, and also receives the input signal. The second unit shifts the input signal to the higher supply voltage output signal. The level shifter operates only at the high power supply voltage.

Claims

1. A level shifter that shifts a low supply voltage input signal to a higher supply voltage output signal, the level shifter comprising:

a first unit connected to a high power supply voltage source and receiving the input signal, the first unit acting as a startup circuit such that when the level shifter is powered on, the first unit discharges an output node if the input signal is a logic low; and

a second unit connected to the first unit and the high power supply voltage source, and receiving the input signal, wherein the second unit shifts the input signal to the higher supply voltage output signal, and wherein the level shifter operates only at the high power supply voltage, wherein the first unit includes;

a first NMOS transistor having source connected to the input signal, a bulk connected to a reference voltage, a drain connected to the second unit at the output node, and a gate; and

a pair of series connected transistors, including a first series transistor and a second series transistor, wherein the first series transistor has a source and a bulk connected to the reference voltage, a drain connected to the gate of the first NMOS transistor at the control node, and a gate connected to its drain, and the second series transistor has a source connected to the control node, a bulk connected to its source, a drain connected to the second unit, and a gate connected to its drain.

2. The level shifter according to claim 1, wherein the second unit comprises:

a second NMOS transistor having a source connected to the reference voltage, a drain connected to the output node, and a gate;

a third NMOS transistor having a gate connected to the input signal, a source connected to the reference voltage, and a drain connected to the gate of the second NMOS transistor;

a second PMOS transistor having a drain connected to the drain of the second NMOS transistor at the output node, a source connected to the high power supply voltage source and the drain of the second series transistor, and a gate; and

a third PMOS transistor having a source connected to the high power supply voltage source, a drain connected to the gate of the second PMOS transistor and the drain of the third NHOS transistor, and a gate connected to the output node.

3. A level shifter that shifts a low supply voltage input signal to a higher supply voltage output signal, the level shifter comprising:

a first NMOS transistor having a source connected to the input signal, a bulk connected to a reference voltage, and a drain connected to an output node;

a first PMOS transistor having a source connected to the input signal, a drain connected to a gate of the first NMOS transistor at a control node, and a bulk connected to a high power supply voltage source;

a capacitor having a first terminal connected to the high power supply voltage source and a second terminal connected to the gate of the first NMOS transistor and the drain of the first PMOS transistor at the control node;

a second NMOS transistor having a source connected to the reference voltage, a drain connected to an output node, and a gate connected to a gate of the first PMOS transistor at an inverted output node;

a third NMOS transistor having a gate connected to the input signal, a source connected to the reference voltage, and a drain connected to the gate of the second NMOS transistor;

a second PMOS transistor having a drain connected to the drain of the second NMOS transistor at the output node, and a source connected to the high power supply voltage source; and

a third PMOS transistor having a source connected to the high power supply voltage source, a drain connected to a gate of the second PMOS transistor and the drain of the third NMOS transistor, and a gate connected to the output node.

4. A level shifter that shifts a low supply voltage input signal to a higher supply voltage output signal, the level shifter comprising:

a first PMOS transistor having a source and a bulk connected to a high power supply voltage source, and a gate connected to its drain;

a second PMOS transistor having a source and a bulk connected to the drain of the first PMOS transistor, and a gate connected to its drain;

a third PMOS transistor having a source and a bulk connected to the drain of the second PMOS transistor, and a gate connected to its drain;

a fourth PMOS transistor having a source and a bulk connected to the drain of the third PMOS transistor, and a gate connected to the input signal;

a first NMOS transistor having a source and a bulk connected to a reference voltage, a drain connected to a drain of the fourth PMOS transistor, and a gate connected to the input signal and the gate of the fourth PMOS transistor;

a fifth PMOS transistor having a gate connected to the reference voltage, a source connected to the gate of the third PMOS transistor, a bulk connected to its source, and a drain connected to its source;

a second NMOS transistor having a source and a bulk connected to the reference voltage, and a gate connected to the input signal;

a third NMOS transistor having a source and a bulk connected to the reference voltage, and a gate connected to the drain of the fourth PMOS transistor;

a sixth PMOS transistor having a source and a bulk connected to the high power supply voltage source, and a drain connected to the drain of the second NMOS transistor;

a seventh PMOS transistor having a source and a bulk connected to the high power supply voltage source, a drain connected to the drain of the third NMOS transistor and a gate of the sixth PMOS transistor at an output node, and a gate connected to the drain of the sixth PMOS transistor; and

an eighth PMOS transistor having a source and a bulk connected to the high power supply voltage, a drain connected to the gate of the third NMOS transistor, and a gate connected to the drain of the third NMOS transistor, wherein the higher power supply voltage signal is provided at the output node.